Design and Simulate SerDes Systems
High-speed electronic systems suffer from signal degradation caused by various impairments such as impedance mismatch, attenuation, and crosstalk. Using the equalization and gain modulation blocks in the SerDes Toolbox™, you can compensate for the distortions introduced by the lossy channels.
Starting with the SerDes Designer app, you can design the top-level SerDes systems and perform statistical analysis. Use the building blocks and system objects to design, configure, simulate and analyze the SerDes system including the transmitter and the receiver.
|SerDes Designer||Design and analyze SerDes systems for export to Simulink, MATLAB and IBIS-AMI|
|S-Parameter Fitter||Convert S-Parameter network to impulse response|
|CTLE Fitter||Fit poles and zeros to CTLE transfer functions|
|DFECDR||Decision feedback equalizer (DFE) with clock and data recovery (CDR)|
|CDR||Models a clock data recovery circuit|
|FFE||Models a feed-forward equalizer|
|CTLE||Models continuous time linear equalizer (CTLE)|
|AGC||Automatically adjusts gain to maintain output waveform amplitude|
|VGA||Models a variable gain amplifier|
|SaturatingAmplifier||Models a saturation amplifier|
|IBIS-AMI clock_times||Recover SerDes clock time values from custom DFECDR and CDR|
|PassThrough||Propagates baseband signal without modification|
|Analog Channel||Construct loss model from channel loss metric or impulse response|
|Configuration||Configure system wide settings in SerDes system model|
|Eye Diagram Scope||Display eye diagram of time-domain signal|
|Stimulus||Set waveform generation method and number of symbols to simulate in SerDes model|
|Decision feedback equalizer (DFE) with clock and data recovery (CDR)|
|Minimize intersymbol interference (ISI) at clock sampling times|
|Performs clock data recovery function|
|Models a feed-forward equalizer|
|Continuous time linear equalizer (CTLE) or peaking filter|
|Automatically adjusts gain to maintain output waveform amplitude|
|Models a variable gain amplifier|
|Models a saturating amplifier|
|Propagates baseband signal without modification|
|Create simple lossy transmission line model|
|Set a pseudorandom binary sequence (PRBS) pattern and number of symbols to simulate in SerDes model|
|Convert S-parameter to impulse response|
|Pulse response metric for optimization routines|
|Pseudorandom binary sequence|
|Step response from impulse response|
|Pulse response from impulse response|
|Impulse response from step response|
|Impulse response from pulse response|
|Statistical eye from pulse response|
|Peak distortion analysis eye from pulse response|
|Data pattern waveform from pulse response|
|Pulse response from data pattern waveform|
- Design SerDes System and Export IBIS-AMI Model
Create and analyze a SerDes system, and export an IBIS-AMI model using the SerDes Designer app.
- Clock and Data Recovery in SerDes System
Explore the behavior, control and characteristics of a first order clock data recovery (CDR).
- Phase Detectors: Baud-Rate Type-A versus Bang-Bang
To successfully send and receive data between a SerDes transmitter and receiver requires a myriad of conditions to be satisfied.
- Statistical Analysis in SerDes Systems
Customize and explore the statistical analysis of SerDes systems.
- Jitter Analysis in SerDes Systems
Inject Jitter into link analysis and equalization design.
- Analog Channel Loss in SerDes System
Define the loss model to represent the analog channel in a SerDes system.
- Linux Version Compatibilities
Generate shared objects on compatible Linux versions.