What Is Hardware Design?

Hardware design is the process by which functionality is programmed into custom circuitry. System and algorithm developers often begin hardware design in Simulink^® and MATLAB^® and then write a specification document that a hardware design team uses to manually create a hardware description language (HDL) implementation. The HDL representation is then used to program FPGA or ASIC hardware, which is often part of a system on chip (SoC).

Manual writing of low-level HDL limits how broadly the hardware design team can explore different architectures, increases the number of bugs introduced, and limits the ability to reuse the algorithm for other projects.

You can use MATLAB and Simulink to explore algorithms and determine which ones are most compute-intensive and could benefit from hardware design. You can then simulate the SoC architecture using SoC Blockset™.

Hardware Design Refinement

You can also refine the hardware design through several steps, each of which can be verified against the previous step or the original algorithm:

Adapt algorithms to process a continuous stream of data, which is how data typically flows through a hardware design
Trade off numerical accuracy versus efficiency via fixed-point quantization or floating-point implementation of hardware design components
Add micro-architectures such as parallelism, timing, feedback loops, and other functionalities required to implement the hardware design

A diagram showing incremental refinement of designs in MATLAB and Simulink, with verification at each incremental stage. — Schematic of digital algorithm refinement for hardware design, with verification at each step.

You can refine the hardware design using HDL-supported blocks and functions in Simulink and MATLAB. You can also use off-the-shelf libraries of optimized IP for signal processing, wireless, video/image processing, and deep learning applications. Many developers use various combinations of all of these, depending on the application’s needs.

Hardware Design Verification

You can verify each step in the process versus the previous step or the original algorithm. You can reuse any of the representations to help the hardware design team verify their handwritten HDL code, via techniques such as HDL cosimulation or verification component generation. You can also prototype the hardware-ready implementation model on FPGA or SoC hardware connected to MATLAB or Simulink by running FPGA-in-the-loop testing.

Code Generation for Hardware Design

In a fully connected hardware design workflow, you can use HDL Coder™ to generate functionally correct Verilog, SystemVerilog, or VHDL code to begin the hardware design implementation process. This approach has the added advantage of full traceability back to the model and requirements, which is critical for functional safety workflows such as DO-254, ISO^® 26262, and IEC 61508.

Examples and How To

Applications

Field-Oriented Control of a Permanent Magnet Synchronous Machine on a Xilinx Zynq Platform - Example
HDL OFDM Receiver - Example
HDL Implementation of Digital Predistorter - Example
Design Video Processing Algorithms for HDL in Simulink - Example
Increase Image Resolution Using VDSR Network Running on FPGA - Example

Software Reference

Model and Architecture Design - Documentation
HDL Code Generation - Documentation
Verification with Cosimulation - Documentation
Verification with UVM and SystemVerilog Components - Documentation
Fixed-Point and Floating-Point Basics - Documentation
Native Floating Point - Documentation

Hardware Design FAQs

You can use MATLAB and Simulink to model and simulate the algorithm content of digital designs along with the surrounding environment, then use HDL Coder to generate synthesizable HDL from these high-level models for use in FPGA and ASIC implementation workflows.

You can use HDL Coder to generate functionally correct Verilog, SystemVerilog, or VHDL code directly from your models, with full traceability back to the model and requirements for functional safety workflows.

You can adapt algorithms to process streaming data, optimize numerical accuracy through fixed-point quantization, and add select micro-architectures to address issues such as parallelism, timing, and feedback.

You can verify each step against the previous step or original algorithm using HDL cosimulation, verification component generation, or FPGA-in-the-loop testing with hardware connected to a host computer simulating testbench models MATLAB or Simulink.

Yes, MATLAB and Simulink include off-the-shelf libraries of optimized IP for signal processing, wireless, video/image processing, and deep learning applications that you can use with HDL-supported blocks and functions.

You can target FPGA, ASIC, and programmable SoC hardware for various applications including motor control, wireless communications, video processing, and deep learning implementations.

Using MATLAB and Simulink allows broader exploration of different architectures, reduces bugs, enables algorithm reuse across projects, and provides full traceability for functional safety standards such as DO-254, ISO 26262, and IEC 61508.

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