HDL Verifier

MAJOR UPDATE

 

HDL Verifier

Find RTL bugs and generate testbenches for ASICs or FPGAs

ASIC chip mounted on a printed circuit board.

RTL Verification of ASICs and FPGAs

Verify HDL code with MATLAB and Simulink testbenches through cosimulation with simulators from Cadence®, Synopsys®, Siemens®, and AMD®. Generate testbenches for SystemVerilog verification environments.

Simulation-Based Verification

Verify HDL code using MATLAB and Simulink models as testbenches. Incorporate legacy HDL code into system simulations through cosimulation with Xcelium™, VCS®, Questa, and Vivado HDL simulators.

Hardware-Assisted Verification

Connect your host computer automatically to AMD, Altera, and Microchip FPGA boards to verify implementation using MATLAB and Simulink testbenches. Probe internal signals within designs for hardware debugging.

Block diagram of a mixed-signal model.

Mixed-Signal Design and Verification

To evaluate how a design under test interacts with analog circuits, create behavioral models as stand-ins for analog functionality by generating SystemVerilog DPI-C code from analog or mixed-signal models from Simscape™, SerDes Toolbox™, or Mixed-Signal Blockset™.

Diagram illustrating SystemVerilog testbench generation.

Generate RTL Testbenches

Use ASIC Testbench to generate SystemVerilog DPI components from MATLAB functions or Simulink subsystems for use in functional verification environments, including VCS, Xcelium, Questa, and Vivado.

MATLAB: Documentation | Examples

Simulink: Documentation | Examples

Diagram illustrating Universal Verification Methodology testbench generation.

Generate UVM Environments

Use ASIC Testbench to generate complete Universal Verification Methodology (UVM) testbenches for HDL simulators from MATLAB and Simulink. Generate fully functional testbenches for the UVM Framework (UVMF).

Debug on Development Boards

Capture high-speed signals from designs executing on an FPGA and automatically load them into MATLAB for visualization and analysis. Use the Logic Analyzer app to explore signals throughout your design when verifying expected behavior or investigating anomalies.

Diagram illustrating SystemC TLM 2.0 generation.

Generate SystemC TLM 2.0 Transaction-Level Models

Use ASIC Testbench to generate SystemC virtual prototype models with TLM 2.0 interfaces for use in virtual platform simulations. Use TLM generation to produce IP-XACT files with mapping information between Simulink and generated TLM components.

“With this model-based verification approach, we benefit from early functional verification in Simulink and a system-level view of the design that facilitates collaboration between systems engineers and verification teams. Early model verification leads to better quality HDL because high-level design and requirements issues are found and eliminated before code generation. We expect this early bug detection to save two months of verification effort.”