HDL Verifier enables you to reuse your system-level design environment in your HDL design environment. You can test and verify RTL designs against golden reference models in MATLAB and Simulink, debug designs in simulators or hardware, and generate testbenches and verification IP.
With HDL Verifier, you can verify FPGA, ASIC, and SoC designs using testbenches that run in MATLAB and Simulink with RTL designs that run in your HDL simulator. You can reuse these testbenches with AMD®, Altera®, and Microchip FPGA development boards to verify hardware implementations and probe internal signals to debug designs. You can also generate Universal Verification Methodology (UVM) components from MATLAB and Simulink for use in your SystemVerilog verification environment. All these capabilities are compatible with existing HDL code and code generated by HDL Coder.
RTL Verification of ASICs and FPGAs
Verify HDL code with MATLAB and Simulink testbenches through cosimulation with simulators from Cadence®, Synopsys®, Siemens®, and AMD®. Generate testbenches for SystemVerilog verification environments.
Simulation-Based Verification
Verify HDL code using MATLAB and Simulink models as testbenches. Incorporate legacy HDL code into system simulations through cosimulation with Xcelium™, VCS®, Questa, and Vivado HDL simulators.
Hardware-Assisted Verification
Connect your host computer automatically to AMD, Altera, and Microchip FPGA boards to verify implementation using MATLAB and Simulink testbenches. Probe internal signals within designs for hardware debugging.
Mixed-Signal Design and Verification
To evaluate how a design under test interacts with analog circuits, create behavioral models as stand-ins for analog functionality by generating SystemVerilog DPI-C code from analog or mixed-signal models from Simscape™, SerDes Toolbox™, or Mixed-Signal Blockset™.
Examples (SerDes Toolbox, Mixed-Signal Blockset)
Generate RTL Testbenches
Use ASIC Testbench to generate SystemVerilog DPI components from MATLAB functions or Simulink subsystems for use in functional verification environments, including VCS, Xcelium, Questa, and Vivado.
MATLAB: Documentation | Examples
Simulink: Documentation | Examples
Generate UVM Environments
Use ASIC Testbench to generate complete Universal Verification Methodology (UVM) testbenches for HDL simulators from MATLAB and Simulink. Generate fully functional testbenches for the UVM Framework (UVMF).
Debug on Development Boards
Capture high-speed signals from designs executing on an FPGA and automatically load them into MATLAB for visualization and analysis. Use the Logic Analyzer app to explore signals throughout your design when verifying expected behavior or investigating anomalies.
Generate SystemC TLM 2.0 Transaction-Level Models
Use ASIC Testbench to generate SystemC virtual prototype models with TLM 2.0 interfaces for use in virtual platform simulations. Use TLM generation to produce IP-XACT files with mapping information between Simulink and generated TLM components.
Product Resources:
“With this model-based verification approach, we benefit from early functional verification in Simulink and a system-level view of the design that facilitates collaboration between systems engineers and verification teams. Early model verification leads to better quality HDL because high-level design and requirements issues are found and eliminated before code generation. We expect this early bug detection to save two months of verification effort.”
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