SoC Blockset

Design, evaluate, and implement SoC hardware and software architectures


SoC Blockset™ provides Simulink® blocks and visualization tools for modeling, simulating, and analyzing hardware and software architectures for ASICs, FPGAs, and systems on a chip (SoC). You can build your system architecture using memory models, bus models, and I/O models, and simulate the architecture together with the algorithms.

SoC Blockset lets you simulate memory and internal and external connectivity, as well as scheduling and OS effects, using generated test traffic or real I/O data. You can quickly explore different system architectures, estimate interface complexity for hardware and software partitioning, and evaluate software performance and hardware utilization.

SoC Blockset exports reference designs for Xilinx® and Intel® FPGA devices and SoC platforms, including Zynq®-7000, Ultrascale+™, and Intel SoC FPGAs. These reference designs can be used with Xilinx and Intel design tools.

Get Started:

Simulate and Analyze SoC Architectures

Develop and combine software algorithms, hardware logic, memory systems, and I/O devices into your SoC application. Evaluate architecture alternatives before deploying to hardware.

Analyze Algorithm Resource Usage

Analyze Simulink models or MATLAB functions to generate reports summarizing the number of arithmetic operators required for implementation. Use these reports to compare different architectures, perform design tradeoffs, and explore hardware/software partitioning.

View the estimated number and type of operators needed to implement MATLAB functions or Simulink models.

Memory Transactions

Model and simulate shared memory transactions between hardware logic and embedded processors. Configure DMA memory controllers to arbitrate memory traffic. Account for memory latency and throughput in simulation.

Task Execution

Model task execution in an embedded process as managed by the operating system (OS). Simulate tasks with accurate timing, accounting for context switching, task preemption, and execution duration.

Visualize task preemption, context switching, and execution duration with timing diagrams.

SoC Model Templates

Build complete models of SoC applications from scratch using a step-by-step approach, or start from predefined templates for hardware/software coprocessing, including templates for vision and communication applications.

Build models for SoC applications using predefined model templates.

Simulation with Recorded I/O Data

Record hardware peripheral sources such as RF signals or HDMI data, and then play back recordings as sources in simulations or hardware testing.

Play back recordings as a source for simulation.

Analyze System Performance

Evaluate memory performance and task execution through simulation and perform on-device profiling.

Task Execution Analysis

Simulate the software system of SoC applications by running Simulink models that incorporate timer-driven and event-driven tasks. Visualize task execution timing, preemption, rate overruns, drops, and core utilization. Replay task executions in simulation using task timing data captured from previous simulations or directly from SoC devices.

Perform statistical analysis of task execution times.

DDR Memory Performance

Analyze the memory bandwidth of system designs. Visualize simulation results and bandwidth metrics before deploying to the SoC device.

Simulate shared memory transactions and analyze performance.

On-Device Memory Performance Monitoring and Task Execution Profiling

Measure memory performance and task execution on an SoC device, and then visualize and analyze these measurements to tune an SoC model to meet your system performance requirements. Interact in real time with SoC devices from MATLAB or from your Simulink test bench.

Measure task execution with code instrumentation profiler.

Deploy to SoC and FPGA Devices

Generate reference designs and RTL code for programmable logic. Generate C/C++ code for processor tasks.

Generate Embedded Software Project

When used with Embedded Coder®, SoC Blockset generates complete embedded software projects from models, including schedulers, software tasks, and I/O device driver integration.

Generate complete embedded software projects from models.

Generate Reference Designs

Generate reference designs for programmable logic. Reference designs are configured networks of IP cores with data and control paths that may be connected to external memories and software applications. SoC Blockset connects to Xilinx and Intel design tools to produce bitstreams and then programs FPGA and SoC boards.

Generate reference designs for use with HDL algorithm IP.

Generate Algorithm IP

Generate target-optimized algorithm IP with HDL Coder™. Integrate the generated IP into the reference designs exported from SoC Blockset, and use FPGA vendor tools to produce complete bitstreams.

Generate algorithm IP into reference designs with HDL Coder.

Generate Application Software

Using Embedded Coder, generate software application code and deploy it to an SoC hardware board. SoC Blockset automatically creates tasks; assigns them to threads; and links interrupts, messages, and system events to the generated code.

Generate application software from algorithm model.

Target COTS boards and Custom Boards

Implement hardware/software applications on supported hardware kits including Xilinx Zynq UltraScale+ MPSoCs and RFSoCs, Zynq-7000 SoCs and Intel Cyclone and Arria SoC FPGAs. Target boards using hardware support packages or build support for custom boards.

Explore gallery (4 images).

Latest Features

Reference Designs

Export custom reference designs from your SoC Blockset Simulink model

Algorithm Analyzer

Analyze the computational complexity of MATLAB functions or Simulink models early in the design process

Proxy Task block enhancement

Model asynchronous task execution for task components with unknow implementation

IP Core Register Read Block

Model write operations from processor to hardware logic

I2C Master Block Enhancements

Extend configuration support to additional slave devices and synchronize with slow-running I2C slave devices

Xilinx UltraScale+ RFSoC support

Simulate the hardware/software architecture of Xilinx RFSoC devices, then deploy applications to the Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit

See release notes for details on any of these features and corresponding functions.

MATLAB for FPGA, ASIC, and SoC Development

Domain experts and hardware engineers use MATLAB® and Simulink® to develop prototype and production applications for deployment on FPGA, ASIC, and SoC devices.