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Algorithm Verification

Execute MATLAB® or Simulink® in sync with FPGA or HDL simulation

Create a communication link between the HDL simulator or FPGA and MATLAB or Simulink.

  • FPGA-in-the-Loop (FIL) enables you to run a Simulink or MATLAB simulation that is synchronized with an HDL design running on an Intel®, Microchip, or AMD® FPGA board.

  • HDL Cosimulation enables you to run a Simulink or MATLAB simulation that is synchronized with an HDL design simulating with an HDL simulator.

These features enable you to:

  • Verify a model directly against the HDL implementation.

  • Create test signals and testbenches for HDL code.

  • Use a behavioral model as a reference in an HDL simulation.

  • Use analysis and visualization features for real-time insight into an HDL implementation.

  • Integrate a new model with an existing HDL design.

  • Apply data and test scenarios from MATLAB or Simulink to the HDL design on the FPGA.

These features are not available in MATLAB Online™.

Before you can use FIL simulation, you must download the support package for your board. See Download FPGA Board Support Package.

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