From Algorithms to FPGA / ASIC Implementation with MATLAB and Simulink
Learn about generating HDL code from MATLAB® code and Simulink® models for FPGA and ASIC implementation. This session starts with a brief introduction to Model-Based Design and the hardware development workflow. A MathWorks engineer will then demonstrate the step-by-step process with HDL Coder™ to start from initial models, incorporate hardware-specific constructs, and generate Verilog and VHDL code for FPGAs and ASICs.
- Using Simulink and Model-Based Design for hardware development.
- Converting floating point to fixed point for hardware implementation
- Incorporating MATLAB code into HDL workflows using Simulink
- Prototyping designs on FPGA and SoC development boards
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