Generate SystemVerilog DPI Component from verify Statement

You can generate a SystemVerilog DPI component from Simulink® Test™ verify statements. When using the Test Assessment or Test Sequence blocks, you can assess model behavior by including verify statements in the test sequence. To map the verify statements to a SystemVerilog assertion, generate a SystemVerilog DPI component from the Test Assessment or Test Sequence block. Use the SystemVerilog DPI component in your HDL test environment.

Create a Simulink Test Sequence

In Simulink, create a model for the device under test (DUT), and create a test bench for the model using Test Assessment or Test Sequence blocks. Use the Test Sequence Editor (Simulink Test) to create and edit test steps. In the test sequence, use verify statements to assess the simulation, as described in Test Sequence and Assessment Syntax (Simulink Test).


The verify statement along with the Test Sequence block represents a temporal check in Simulink. When generating a SystemVerilog DPI component, the temporal logic is located in the generated C code. The SystemVerilog wrapper contains an immediate assertion that triggers when the verify condition is violated.

When simulating your design in Simulink, the simulation emits a warning if the verify assessment fails.

You can view and inspect the simulation results by using the Simulation Data Inspector. Open the Simulation Data Inspector by entering this code at the MATLAB® command line.

To view signals over time, select them in the left pane of the Simulation Data Inspector.

Generate a SystemVerilog DPI Component for a verify Statement

Configure the Model for Code Generation

In the Configuration Parameters dialog box, select Code Generation in the left pane. Under Target Selection, set System Target File to systemverilog_dpi_grt.tlc, or alternatively to systemverilog_dpi_ert.tlc when using Embedded Coder®.

Select SystemVerilog DPI in the left pane. Under SystemVerilog Ports,set the data type and connection settings. Click OK.

Generate a SystemVerilog DPI Component


To generate a DPI Component, the Test Assessment block or Test Sequence block must be inside a Simulink subsystem.

In Simulink, right-click on the subsystem block, which contains the test sequence, and select C/C++ Code > Build This Subsystem. Click Build in the dialog box that opens.

Command-line alternative: Use the rtwbuild function to build the system. For example, to build a subsystem named "My_verify_tst", enter this code at the MATLAB command line.


Run an HDL Simulation with the Generated Component

Change your current folder to the dpi_tb folder, which is under the code generation folder in your HDL simulator installation. Start your HDL simulator, and run the generated script to start the simulation. The simulation output is consistent with the Simulink output.

For additional information on running the HDL simulation, see Verify Generated Component Against Simulink Data.

Trace Generated SystemVerilog Error Back to Simulink Source

After running a SystemVerilog simulation with a generated test sequence, your log file displays warnings and errors. To identify which block originated a specific warning or error output, use the Simulink Identifier (SID) hilite function.

Each generated error or warning displays a unique name identifying its origin. That number is the SID of that block. For example, the output in the previous figure shows an error that was generated by a test sequence block with SID Req_scenario_4:32:60.

# ** Error: Req_scenario_4:32:60: At step 'Check2' verify id 'Simulink:verify_sc4_off' Failed

To highlight the block that generated this warning, enter this code at the MATLAB command line.


The figure highlights both the verify statement and the test sequence block that created this warning.

For additional information about Simulink Identifiers, see Locate Diagram Components Using Simulink Identifiers (Simulink).

Verbose Mode

By default, the generated DPI component outputs an error when the verify assessment is tested and fails. To see additional output generated by the verify assessment, use the argument +VERBOSE_VERIFY in the HDL simulation command line. This argument adds information showing when the verify assessment was not tested, and when it was tested and passed. For example, when using ModelSim® enter the following at the command line.

vsim -classdebug -c -voptargs=+acc -sv_lib ../Req_4 work.Req_4_dpi_tb +VERBOSE_VERIFY

This command outputs a verbose log, which includes details about when the verify assessments were tested and whether they passed or failed.

Filter Verify Assessments

You may have several steps in a test sequence that utilize a verify assessment or several DPI components logging warnings from a simulation. In your test model, you can filter the generated output for specific verify steps by specifying the associated SID as a plus argument on the command line. For example, to turn off all output for SID Req_scenario_4:32:60, enter this code at the HDL command line.

vsim -classdebug -c -voptargs=+acc -sv_lib ../Req_4 work.Req_4_dpi_tb +Req_scenario_4:32:60

See Also


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