Check Dynamic Upper Bound

Check that one signal is always greater than another signal

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Libraries:
Simulink / Model Verification
HDL Coder / Model Verification

Description

The Check Dynamic Upper Bound block checks if the reference signal, max, is greater than the amplitude of an input signal, u, at each time step and executes an assertion after comparison. If max is greater than u, the assertion is true (1) and the block does nothing. If not, the block halts the simulation and returns an error message by default.

The input signals can be scalars, vectors, or matrices. Both input signals must be the same data type. The block compares the value of u to max differently depending on the signal.

• When comparing scalars to vectors or matrices, the block compares the scalar signal to each element of the non-scalar signal.

• When comparing a vector or matrix signal to another vector or matrix signal, the block checks the signals element-by-element.

• For models with an input signal and bound that are both vectors or matrices, the input signal and bound must have the same dimensions.

Examples

Check Signal Upper Bound with Check Dynamic Upper Bound Block

Using the Check Dynamic Upper Bound block, you can check if an input signal rises above a changing upper bound during a simulation.

In this example, the Check Dynamic Upper Bound block compares the value of a tested input signal from a Step block at the u port to a Sine Wave block at the max port. The Check Dynamic Upper Bound block checks if the value of the signal at the max port is greater than the value of the tested input signal. If it is, the block asserts true (1). Because the Output assertion signal parameter of the Check Dynamic Upper Bound block is selected, the block outputs the assertion value. Run the simulation to observe the model output.

At the start of the simulation, the Check Dynamic Upper Bound block outputs 1 because the value of the Sine Wave block is greater than the value of the Step block. At a time of 3.14, the sine wave dips below 0, causing the value of the Step block to exceed the sine wave. The Check Dynamic Upper Bound block recognizes this change and outputs 0.

At a time of 5, the Step block outputs a value of 0.5, which is still greater than the sine wave. The Step block value stays greater than the sine wave until the time reaches 6.81. The Check Dynamic Upper Bound block recognizes this change and the assertion passes. The output stays at 1 until the time reaches 8.90, where the sine wave goes below the value of the Step block.

Ports

Input

max — Upper bound of range check

scalar | vector | matrix

Signal specifying the lower bound of the range that the block checks the input signal u amplitude. Signal data type and dimension must be the same as u.

Data Types: half | single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated

u — Input signal checked against bound

scalar | vector | matrix

Input signal checked against the lower bound specified by min.

Data Types: half | single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | Boolean | fixed point | enumerated

Output

Port_1 — Assertion output signal

scalar

Output signal that is true (1) if the assertion succeeds and false (0) if the assertion fails. If, in the Configuration Parameters window, in the Math and Data Types section, under Advanced parameters, you select Implement logic signals as Boolean data, then the output data type is Boolean. Otherwise, the data type of the signal is double.

Dependencies

To enable this output port, select the Output assertion signal parameter check box.

Data Types: double | Boolean

Parameters

Enable assertion — Enable or disable check

on (default) | off

Clearing this parameter disables the block and causes the model to behave as if the block does not exist. To enable or disable all verification blocks, regardless of the setting of this option, go to the Configuration Parameters window, click Diagnostics > Data Validity, expand the Advanced parameters section, and set Model Verification block enabling to Enable all or Disable all.

Programmatic Use

Parameter: enabled

Type: string scalar or character vector

Values: "on" | "off"

Default: "on"

Simulation callback when assertion fails (optional) — Expression to evaluate when assertion fails

"" (default) | MATLAB expression

Specify a MATLAB^® expression to evaluate when the assertion fails. Because the expression is evaluated in the MATLAB workspace, define all variables used in the expression in that workspace.

Dependencies

To enable this parameter, select Enable assertion.

Programmatic Use

Parameter: callback

Type: string scalar or character vector

Default: ""

Stop simulation when assertion fails — Whether to stop simulation when check fails

on (default) | off

Select this parameter to stop the simulation when the check fails. Clear this parameter to display a warning and continue the simulation.

Programmatic Use

Parameter: stopWhenAssertionFail

Type: string scalar or character vector

Values: "on" | "off"

Default: "on"

Output assertion signal — Create output signal

off (default) | on

Select this parameter to enable the output port.

Programmatic Use

Parameter: export

Type: string scalar or character vector

Values: "on" | "off"

Default: "off"

Select icon type — Select icon type

graphic (default) | text

Specify the style of the block icon. The graphic option displays a graphical representation of the assertion condition on the icon. The text option displays a mathematical expression that represents the assertion condition.

Programmatic Use

Parameter: icon

Type: string scalar or character vector

Values: "graphic" | "text"

Default: "graphic"

Block Characteristics

Data Types	Boolean | double | enumerated | fixed point | half | integer | single
Direct Feedthrough	no
Multidimensional Signals	yes
Variable-Size Signals	no
Zero-Crossing Detection	no

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

For information about how Simulink^® Coder™ generated code handles Model Verification blocks, see Configure Model for Debugging (Simulink Coder).

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

Architecture	Description
No HDL	Do not generate HDL code for this block.

HDL Block Properties

PreserveUpstreamLogic

Control the removal of unconnected logic. The default is off, which means unconnected logic is not preserved in HDL code. For more details, see PreserveUpstreamLogic (HDL Coder).

PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced before R2006a