Generate Universal Verification Methodology (UVM) test components and a behavioral design under test (DUT) from a Simulink model. You can use the generated components in two ways.
Generate a UVM top model with a test bench and a behavioral (DUT). Use the generated UVM top module as a test environment, and replace the generated behavioral DUT with your own simulation model.
Generate UVM test components, and integrate them into your existing UVM environment.
This feature requires Simulink Coder™.
|Generate UVM test bench from Simulink model|
If you have a Simulink Coder license, you can generate a Universal Verification Methodology (UVM) test bench and additional components from a Simulink model.