When you generate HDL code using HDL Coder, the tools provide options for automatic verification of the generated code against your source MATLAB® or Simulink® design. Use the HDL Workflow Advisor to guide you through code generation and verification. See Getting Started with the HDL Workflow Advisor (HDL Coder) and Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor (HDL Coder).
You can generate four kinds of test benches for verification of generated code: HDL simulation, cosimulation, FPGA-in-the-loop (FIL), or DPI component. The latter three test benches are provided when you have an HDL Verifier™ license. See Choose a Test Bench for Generated HDL Code (HDL Coder).
Verify generated HDL code using a generated cosimulation model.
Verify generated HDL code using a generated cosimulation script.
Generate an FPGA-in-the-loop model using HDL Workflow Advisor.
Generate an FPGA-in-the-loop System object™ and test bench using HDL Workflow Advisor.
This example shows how to use SystemVerilog DPI test bench for verification of HDL code where a large data set is required.
This example uses HDL cosimulation and FPGA-in-the-loop (FIL) simulation to verify an HDL design comprising generated and legacy HDL code.
This example shows how to verify generated HDL code using HDL Cosimulation and FPGA-in-the-Loop as steps in the HDL code generation workflow for MATLAB® to HDL.
This example shows how to generate HDL code from a MATLAB® design implementing the Sobel edge detection algorithm.
Verification (HDL Coder)