What Is SystemVerilog?
SystemVerilog is both a hardware description language and a hardware verification language. It is used to model, design, simulate, verify, test, and implement algorithms or systems for ASICs and FPGAs/SoCs. SystemVerilog is based on the Verilog language with numerous extensions, and in 2009 it became part of the same IEEE standard as Verilog.
SystemVerilog has long been used for the development of RTL testbenches because of its support for constrained random verification, assertions, and functional coverage, as well as its support for object-oriented programming.
Accelerate Design with SystemVerilog
MATLAB® and Simulink® are widely used for the development of algorithms for implementation in hardware. Automatic generation of SystemVerilog HDL from MATLAB code and Simulink models using HDL Coder™ can accelerate the process of FPGA/SoC and ASIC designs as well as automating generation of RTL testbench components.
SystemVerilog for ASIC and FPGA Code Generation
HDL Coder enables high-level design for FPGAs, SoCs, and ASICs by generating portable, synthesizable SystemVerilog code from MATLAB functions and Simulink models, as well as Stateflow® charts. You can use the generated HDL code for FPGA programming, ASIC prototyping, and production design.
HDL Coder includes a workflow advisor that automates prototyping generated SystemVerilog code on AMD®, Intel®, and Microchip boards and generates IP cores for ASIC and FPGA workflows. You can optimize for speed and area, highlight critical paths, and generate resource utilization estimates before synthesis. HDL Coder provides traceability between Simulink models and generated SystemVerilog code, enabling code verification for high-integrity applications adhering to DO-254 and other standards.
ASIC and FPGA Verification with SystemVerilog DPI
The SystemVerilog Direct Programming Interface (DPI) acts as an interface between a SystemVerilog simulator and foreign programming languages such as C, enabling the reuse of existing C code with leading HDL simulators. Using HDL Verifier™, ASIC and FPGA project teams can generate verification components directly from MATLAB code and Simulink models in the form of SystemVerilog DPI components, such as stimulus, checkers, and behavioral design-under-test (DUT) blocks.
SystemVerilog DPI models generated from MATLAB or Simulink can also be integrated into existing Universal Verification Methodology (UVM) environments.
Generating SystemVerilog DPI Testbenches
- Component testbench: If you generate a C component from a Simulink subsystem for use as a DPI component, you can generate a SystemVerilog testbench. The testbench verifies the generated DPI component against data vectors from your Simulink model. (See Generate SystemVerilog DPI Component.)
- HDL code testbench: If you generate HDL code from a Simulink subsystem using HDL Coder, you can generate a SystemVerilog testbench in the form of a set of vectors. This testbench compares the output of the HDL implementation against the results of the Simulink model captured from simulation runs (See Verify HDL Design Using SystemVerilog DPI Testbench.)