Kiran Kintali
Last seen: Today
MathWorks
329 total contributions since 2011Professional Interests: Signal Processing, FPGAs and ESL Design
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Answer 50 questions that were unanswered for more than 30 days
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Awarded to Kiran Kintali on 21 Jun 2020
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Awarded to Kiran Kintali on 20 Jul 2017
hdl coder work flow adviser block compability error
Running hdlsetup command on the model targeted for FPGA always helps in terms of data type selection. web(fullfile(docroot, 'h...
ungefär 5 timmar ago | 1
hardware implementation of NN code
Do you have access to these products? https://www.mathworks.com/products/gpu-coder.html GPU Coder™ generates optimized CUDA...
4 dagar ago | 0
How to generate hdl code for a function containing dsp.HDLFFT and dsp.HDLIFFT system objects?
Please share sample MATLAB Code and Testbench and the error you are seeing. Thanks
5 dagar ago | 0
How to generate hdl code for a function containing dsp.HDLFFT and dsp.HDLIFFT system objects?
Can you share a sample code and testbench? See attached example on how to generate HDL from hdl.FFT function.
13 dagar ago | 0
can we generate HDL code for matrix multiplication ?
You can do this to open the models. The models do not use any new 20b features. https://www.mathworks.com/help//simulink/gui/si...
14 dagar ago | 0
can we generate HDL code for matrix multiplication ?
Attaching few flavors of matrix multiplication compatible with HDL Coder. matmul_external_memory_20b.slx matmul_mlfb_fixpt_...
26 dagar ago | 0
How can I convert from decimal to binary for HDL Coder?
Attaching the model in the example for convenience.
26 dagar ago | 0
Data type issue for LUT input
hdlcoderFocCurrentFixptHdl should generate HDL out of the box. >> makehdl('hdlcoderFocCurrentFixptHdl/FOC_Current_Control') ...
ungefär en månad ago | 0
hdlcoder std_logic_vector to stateflow type
Attached simple Stateflow chart will generate the code you are looking for.
ungefär en månad ago | 0
can we generate HDL code for matrix multiplication ?
hi satish, can you share more details?are both A and B inputs to the DUT or only one of them, what are the types, are you lookin...
ungefär en månad ago | 0
HDL-Coder AXI-Vector Strobe Register validation model
HDL Coder does not currently support adding additional logic to the validation model.
ungefär 2 månader ago | 1
HDL Coder: How to create a resettable delay that triggers on rising edge
Please find attached two variations of the model generating HDL code. Simulink “Counter Limited” block with dynamic upper limit...
ungefär 2 månader ago | 0
| accepted
Error with cosimulation on tunable parameters
https://www.mathworks.com/help/supportpkg/xilinxzynqbasedvision/ug/fpga-targeting-workflow.html yes, You can target zed board u...
ungefär 2 månader ago | 0
About hdlsllib/HDL RAMs blocks
>> How can we load data to the RAM or ROM block in simulink?
ungefär 2 månader ago | 0
Error with cosimulation on tunable parameters
This is a limitation in the cosimulation test bench generation. Can you consider using stand-alone testbench with HDL Simulato...
ungefär 2 månader ago | 0
Delay Balancing Error (RTL Code/ IP Core generation)
>> Barry, just to confirm, HDL coder will require disabling delay balancing if the model containts introduced delays inside a fe...
ungefär 2 månader ago | 0
HDL Coder Error: BITAND/BITOR/BITXOR must have matching operand types
HDL Coder team believes this issue has been resolved in the latest releases. Can you share a sample model? We can double check a...
ungefär 2 månader ago | 1
| accepted
Getting Started with Targeting Xilinx Zynq Platform
(follow up from my team) Hi Kiran, I think I might know the issue. In one of the images, I can see the Tool Version text box...
2 månader ago | 0
Slow simulation time ins simulink.
“How do I model the clock signal?” – is a question frequently asked by hardware engineers who are new to using Simulink and HDL ...
2 månader ago | 0
| accepted
Field oriented control speed controller hdl conversion
Field-Oriented Control of a Permanent Magnet Synchronous Machine In this example you will review a Field-Oriented Control (FOC)...
2 månader ago | 0
| accepted
Getting Started with Targeting Xilinx Zynq Platform
The error essage seems to indicate this is an issue with Xilinx Vivado installation? Task "Vivado IP Packager" unsuccessful. ...
2 månader ago | 0
HDL Workflow Advisor Error from inf SampleTime
This issue is actively resolved. Please reach out to support@mathworks.com for additional support on this issue. Thanks
2 månader ago | 0
HDL coder and Embedded coder interaction
If your target hardware requires you to generate C and HDL code it is better to split your design into two subsystems or two mod...
2 månader ago | 0
| accepted
Sampling rate conversion issues in HDL coder
See attached QPSK Tx, Rx example that works with HDL Coder. You can read through instructions in QPSKTxRxHDLExample.m on how to...
3 månader ago | 0
instrumented MEX function...and HDL code...
The original question is related to floating point to fixed point conversion in MALTAB and is now resolved. The followups respon...
3 månader ago | 0
Simulink HDL coder Results compare
If you continue to face the issue please search for Gain block related HDL Coder bug fix by your release here. https://www.math...
3 månader ago | 0
HDL Coder black box inclusion of module with parameterised packed input
>> I considered just using the Bit Concat block and then using the Extract Bits block within the model of the black box, but tha...
3 månader ago | 0
About HDL simulink coder for StateFlow
Attached model describes how to model either edge in Stateflow suitable for HDL code generation. HDL Verision Result C...
3 månader ago | 0
Fixed point to float point conversion of 16 point ifft
See attached example for additional modeling guidelines for MATLAB to HDL.
3 månader ago | 0
Error creading HDL from subsystem
This is a model compilation issue and not HDL Code generation issue. Press ctrl-d or compile the model and make sure there are n...
3 månader ago | 0
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