How can we tune the Discrete integrator of the HDL Coder for second order generalized integrator for FPGA

Hello Dear all,

I am using the FPGA based SOGI Controller in the HDL Coder. I tried to verifed the different gain values of the discrete inegrator and also tried to verified for different values of the enables signal of the delay block for the integrator. i need to get the output (V_alphag') with the tuned sinusoidal signal value around 340 and another same output (qV_alphag') value with the 90 degree phase shift with the (V_alphag'). Tfpga=10ns.

1. SOGI Controller

2. Discrete integrator block

3.Discrete integrator sybsystem block of the 2nd figure

Answer 1

[Kiran Kintali]

Can you share the model here or via tech support? Thanks