FPGA, ASIC, and SoC Development

R2026b

Automate your workflow—from algorithm development to hardware design and verification

Use MATLAB^® and Simulink^® to develop prototype and production applications for deployment on FPGA, ASIC, and SoC devices. With MATLAB and Simulink, you can:

Model and simulate digital, analog, and software together at a high-level of abstraction.
Convert to fixed point using automated guidance, or generate native floating-point operations for any target device.
Analyze hardware and software architectures by modeling memories, buses, and I/Os.
Generate optimized, readable, and traceable VHDL^®, Verilog^®, or SystemVerilog for implementation in digital logic.
Generate processor-optimized C/C++ code to target embedded processors.
Verify your algorithm running in an HDL simulator or on an FPGA or SoC device connected to your MATLAB or Simulink test bench.

A four-stage workflow, with the following stages: 1. modeling and simulation, 2. code generation, 3. verification, and 4. deployment.

Products for FPGA, ASIC, and SoC Development

HDL Coder

Generate Verilog, SystemVerilog, and VHDL code for FPGA and ASIC designs

HDL Verifier

Verify ASIC and FPGA designs with HDL cosimulation and generated testbenches

Deep Learning HDL Toolbox

Prototype and deploy deep learning networks on FPGAs and SoCs

Wireless HDL Toolbox

Design and implement wireless communications subsystems for FPGAs, ASICs, and SoCs

Vision HDL Toolbox

Design image processing, video, and computer vision systems for FPGAs and ASICs

DSP HDL Toolbox

Design digital signal processing applications for FPGAs, ASICs, and SoCs

Fixed-Point Designer

Model and optimize fixed-point and floating-point algorithms

SoC Blockset (for AMD)

Develop applications for AMD Versal and Zynq Adaptive SoCs and FPGAs

Topics

Modeling and Simulation

Use Simulink Templates for HDL Code Generation (HDL Coder)
Use Simulink model templates for HDL code generation to create efficient hardware designs.
Transmit and Receive Tone Using AMD RFSoC Device - Part 1 System Design (SoC Blockset)
Design and simulate data path using SoC Blockset™ for AMD on Xilinx^® RFSoC device.
Wireless Communications Design for ASICs, FPGAs, and SoCs (HDL Coder)
Design wireless communication algorithms for hardware by using Wireless HDL Toolbox™ blocks.
Implement Digital Downconverter for FPGA (DSP HDL Toolbox)
Design a digital downconverter (DDC) for LTE on FPGAs.
Introduction to Custom OFDM (Wireless HDL Toolbox)
This example shows the design and verification of a transmitter and receiver for a custom OFDM communication system that is suitable for HDL code generation. (Since R2024b)
Convert MATLAB Vision Algorithm to Hardware-Targeted Simulink Model (Vision HDL Toolbox)
Create a hardware-targeted design in Simulink that implements the same behavior as a MATLAB reference design.

Code Generation

Basic HDL Code Generation Workflow (HDL Coder)
Follow the workflow for HDL code generation and FPGA synthesis from MATLAB and Simulink algorithms.
Introduction to Optimizations in HDL Coder (HDL Coder)
Learn about speed and area optimizations and how to optimize your design.
Prototype Deep Learning Networks on FPGA and SoC Devices (Deep Learning HDL Toolbox)
Accelerate the prototyping, deployment, design verification, and iteration of your custom deep learning network running on a fixed bitstream by using the dlhdl.Workflow object.

HDL Verification

Get Started with Simulink HDL Cosimulation (HDL Verifier)
Set up an HDL Verifier™ application using the Cosimulation Wizard in the Simulink® environment.
FPGA-in-the-Loop Simulation (SoC Blockset)
FPGA-in-the-loop (FIL) simulation provides the capability to use Simulink or MATLAB software for testing designs in real hardware for any existing HDL code.
Data Capture Workflow (SoC Blockset)
Capture signal data from a design running on an FPGA.
Access FPGA Memory Using JTAG-Based AXI Manager (SoC Blockset)
Use JTAG-based AXI manager to access memories connected to an FPGA.
UVM Component Generation Overview (HDL Verifier)
Generate a Universal Verification Methodology (UVM) environment from a Simulink model.
Generate SystemVerilog DPI Component (HDL Verifier)
Generate a DPI component from Simulink, and explore various configuration parameters.
Verify Generated HDL Code from Simulink Model (HDL Coder)
Generate an HDL test bench to verify the VHDL or Verilog Code.

Deployment

Targeting FPGA and SoC Hardware Overview (HDL Coder)
High-level steps for targeting an FPGA or SoC platform.
Custom IP Core Generation (HDL Coder)
Generate a custom IP core from a model or algorithm using the HDL Workflow Advisor.
Transmit and Receive Tone Using AMD RFSoC Device - Part 2 Deployment (SoC Blockset)
Implement and verify design using SoC Blockset for AMD on Xilinx RFSoC device.

Featured Examples

Streaming Data from Hardware to Software Using AMD SoC Devices

A systematic approach to design the data-path between hardware logic (FPGA) and embedded processor using SoC builder workflow.

(SoC Blockset)

Verify HDL Implementation of PID Controller Using FPGA-in-the-Loop for AMD Devices

Set up an FPGA-in-the-Loop (FIL) application.

(SoC Blockset)

Deploy and Verify YOLO v2 Vehicle Detector on FPGA

Deploy a you only look once (YOLO) v2 vehicle detector on FPGA and verify the end-to-end application using MATLAB.

(Vision HDL Toolbox)

Field-Oriented Control of a Permanent Magnet Synchronous Machine

Generate HDL code for a Field-Oriented Control (FOC) algorithm for a Permanent Magnet Synchronous Machine (PMSM).

(HDL Coder)

Introduction To Custom OFDM Using AMD RFSoC

Design and verify a transmitter and receiver for a custom OFDM communication system by using SoC Blockset for AMD on AMD^® RFSoC device.

(SoC Blockset)

Verify 5G Wireless Applications Using SystemVerilog DPI

Use SystemVerilog DPI components to verify 5G wireless applications in an HDL environment.

(HDL Verifier)