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HDL Verifier

Test and verify Verilog and VHDL using HDL simulators and FPGA boards

HDL Verifier™ lets you test and verify VHDL® and Verilog® designs for FPGAs, ASICs, and SoCs. You can verify RTL with testbenches running in MATLAB® or Simulink® using cosimulation with Siemens® Questa™ or ModelSim™, Cadence® Xcelium™, Synopsys® VCS®, and the AMD® Vivado® simulator. You can reuse these same testbenches with FPGA development boards to verify hardware implementations.

HDL Verifier generates SystemVerilog verification models for RTL testbenches and complete Universal Verification Methodology (UVM) environments. These models run natively in the Questa, Xcelium, VCS, and Vivado simulators via the SystemVerilog Direct Programming Interface (DPI).

HDL Verifier provides tools for debugging and testing implementations on AMD, Intel®, and Microchip boards from MATLAB. You can insert probes into designs and set trigger conditions to upload internal signals into MATLAB for visualization and analysis.

Workflow chart showing HDL Verifier on the left, with arrows leading to three workflows: 1. Algorithm Verification, 2. FPGA debug, 3. Verification IP Export

Get Started

Learn the basics of HDL Verifier

Algorithm Verification

Execute MATLAB or Simulink in sync with FPGA or HDL simulation

FPGA Debug

Debug hardware designs by connecting an FPGA board to MATLAB or Simulink

Export of Verification IP

Generate testbenches for ASIC and advanced FPGA designs

Verification of Generated HDL Code

Generate testbenches to verify HDL code generated with HDL Coder™

HDL Verifier Supported Hardware

Support for third-party hardware, such as AMD, Intel, and Microchip FPGA and SoC devices