Main Content

Generate and Integrate Test Bench Components for UVM Framework

This example shows how to generate DPI components for UVM sequence, and predictor and integrate into a UVM framework (UVMF) test bench. You design the test bench components in MATLAB®, and generate the DPI components and UVMF compliant YAML corresponding to the sequence and predictor components. You then generate UVMF test bench code compatible with the generated components and run the block level RTL simulations using Questa® simulator.


The UVMF is an open-source package released by Siemens® that provides a code generator to generate infrastructure for the UVM-based verification test benches. For more information, see the documentation shipped with the UVMF installation. You can download the UVMF software from Siemens Verification Academy.

The YAML generation from MATLAB is supported on both Windows® and Linux® platforms. This example illustrates the step by step process on Linux. The supporting scripts and HDL files are contained in the yaml_gen_dpi_predictors_proj project.

Save the example working folder to the exampleWorkingFolder variable.

exampleWorkingFolder = pwd;
project = openProject("yaml_gen_dpi_predictors_proj");

Design Overview

The following figure shows the design you use in this example.


The design is of a digital clock chip that calculates the current time and provides additional capabilities such as setting alarm and timer. The Input/Output signals are as follows:

  • increment — Input signal to the chip. This control signal increments the blocks of hours, minutes, or seconds in the digital clock.

  • decrement — Input signal to the chip. This control signal decrements the blocks of hours, minutes, or seconds in the digital clock.

  • shift — Input signal to the chip. This control signal shifts the active block between hours, minutes, and seconds blocks of the digital clock.

  • done — Input signal to the chip. This control signal indicates that the time set operations using the increment, decrement, and shift signals are done.

  • mode — Input signal to the chip. This control signal configures the mode of the digital clock.

  • valid — Input signal to the chip. This valid signal corresponds to the mode control signal.

  • hours_out — Output signal from the chip. This shows the hours block of the current time.

  • min_out — Output signal from the chip. This shows the minutes block of the current time.

  • sec_out — Output signal from the chip. This shows the seconds block of the current time.

  • alarm_out — Output signal from the chip. This shows a pulse response when the alarm condition is met.

  • timer_out — Output signal from the chip. This shows a pulse response when the timer condition is met.

This figure shows how to set the time using the increment, decrement, and shift signals.


The shift signal puts the clock into Settings mode. It toggles between setting of hours, minutes and seconds in this order, as shown in above figure. Once you set a specific block, you can use the increment and decrement control signals to respectively increase or decrease the value of that block.

Block-Level Verification

This figure illustrates the architecture of a block-level UVMF verification environment for one of the blocks called the mode_set_controller in the digital clock chip.


The different components that are part of the block-level verification environment are as follows:

  • input_agent Active agent that drives the test vectors into the input interface of the design. This agent uses the DPI component for the stimulus MATLAB file as sequence.

  • dpi_predictor Component that uses the DPI code generated from the design subsystem to predict the outputs. This component sends the predicted outputs to the Scoreboard component.

  • output_agent Passive agent that monitors the output interface of the design and transfers the signal information to the Scoreboard component. The UVMF derives the interface information of this agent from the predictor DPI component.

  • Scoreboard Component that compares the actual and expected design outputs received from the output agent and predictor, respectively. This component generates a uvm_error if it detects a comparison mismatch.

Generate Block-Level Verification Environment

The generation of block-level verification environments involves multiple steps that are elaborated in this section. This figure illustrates the end-to-end workflow.


Design and Configure UVMF Test Bench Components

Design Predictor and Sequence Components in MATLAB

Develop MATLAB files whose DPI components are used in the block-level UVMF verification environment shown in the previous section. You can use the predictor and sequence components for a few blocks in the digital clock chip that are part of the supporting scripts for this example.


Create and Configure UVMF Sequence and Predictor Components

To create and configure the svdpiConfiguration and uvmfTestBenchConfiguration objects, execute these steps:

1. Navigate to the dut_dpi/mode_set_controller folder.


2. Create and configure the svdpiConfiguration object for uvmf-sequence ComponentKind:

seq = svdpiConfiguration("uvmf-sequence");
seq.MATLABFunctionName = "mode_set_controller_test";

3. Create and configure the svdpiConfiguration object for uvmf-predictor ComponentKind:

pred = svdpiConfiguration("uvmf-predictor");
pred.MATLABFunctionName = "mode_set_controller";

mode = fi(0, 0, 2, 0);
valid = false;
stc_ack = false;
hms_ack = false;
alarm_ack = false;
timer_ack = false;

pred.InputArgs = {mode, valid, stc_ack, hms_ack, alarm_ack, timer_ack};

4. Create and configure the uvmfTestBenchConfiguration object to generate the UVMF test bench YAML along with the necessary DPI component files:

uvmfObject = uvmfTestBenchConfiguration({pred, seq});

Generate DPI Components and UVMF Compliant YAML

To generate the DPI components for the predictor and sequence files and corresponding UVMF test bench YAML, execute the generateYAMLforUVMFTestBench function.


Generate UVMF Test Bench Code

Set these environment variables:

  • UVMF_HOME – Set this environment variable to the UVMF 2023.1 installation path.

  • MTI_VCO_MODE – Set this environment variable to 64 to use the 64-bit Questa executable for UVMF test bench simulations. Other simulators must be compatible but the workflow is not shown in this example.


Navigate to the uvmfbuild/uvmf_testbench folder.


Execute the yaml2uvmf command by providing the UVMF test bench YAML file as arguments to the yaml2uvmf script.

!$UVMF_HOME/scripts/ uvmftb.yaml

This figure shows the generated folder contents.


Setup Environment and Run RTL Simulations

Execute SH Scripts

UVMF generates the SystemVerilog files to integrate the DPI components (e.g. mode_set_controller_predictor_mtlb.svh and a corresponding SH script ( that replaces the base UVMF test bench files with these generated SystemVerilog files for DPI components. To automate the execution of these scripts use the helper function hExecuteUVMFShellScripts, and pass the path to the uvmf_template_output folder as an input argument.


Navigate back to the project folder.


Set Environment Variables in Generated Setup Script

Find the setup_mode_set_controller_environment_variables script with .source extension in the uvmf_template_output/project_benches/mode_set_controller/sim folder. Update the environment variables in that file by using the hUpdateEnvironmentVariables function. The function also sets the environment variables from MATLAB.


For more information regarding this setup script, see Set Environment Variables in Generated Setup Script section of the Integrate SystemVerilog DPI into UVM Framework Workflow example.

Validate Block Functionality Using RTL Simulations

Execute the block-level simulations in Questa simulator by following these steps.

1. Navigate to the uvmf_template_output/project_benches/mode_set_controller/sim folder.


2. Execute the make command.

!make debug TEST_NAME=DPI_stimgen_test

In the Questa window, enter run -all in the Transcript window. This figure shows the simulation results in Questa.


Navigate back to the example working folder.



This example shows how to generate UVMF compliant YAML along with the necessary DPI components from MATLAB and integrate it into UVMF using yaml2uvmf workflow. The example lays out a step-by-step process to generate the block-level verification environment and then run RTL simulations. You can follow this approach to generate the UVMF environments for other blocks in the digital clock design.

See Also


Related Topics