Prepare Model for Deployment
Prepare a model or MATLAB function for deployment on an FPGA. The input is a Simulink® model or MATLAB function and a chosen hardware platform. The output is a partitioned model specifically designed for deployment for a standalone FPGA, an FPGA on-board an SoC device, or an FPGA I/O board on Simulink Real-Time™ target machine.
For more details on the workflow, see Targeting FPGA & SoC Hardware Overview.
- Model Design for AXI4 Slave Interface Generation
How to design your model for AXI4 or AXI4-Lite interfaces for scalar, vector ports, bus data types, and read back values.
- Map Bus Data types to AXI4 Slave Interfaces
This example shows how to map bus data types to an AXI4 slave interface, generate an HDL IP core with a AXI4 Master interface, perform matrix multiplication in HDL IP core, and write the output result to DDR memory.
- Model Design for AXI4-Stream Interface Generation
How to design your model for AXI4-Stream vector or scalar interface generation.
- Model Design for AXI4-Stream Video Interface Generation
How to design your model for IP core generation with AXI4-stream video interfaces.
- Model Design for AXI4 Master Interface Generation
Description of AXI4 Master protocol, and how you can design your model for IP core generation with AXI4-Master interfaces.
- Model Design for Frame-Based IP Core Generation
How to design your model to use the frame-to-sample optimization for IP core generation.
- Save Target Hardware Settings in Model
This example shows how to save your target hardware settings in a Simulink® model.