Main Content

External Component Interfaces

HDL code instantiation, black box interfaces, Xilinx® System Generator, Altera® DSP Builder, HDL cosimulation

Examples and How To

External HDL Code

Integrate Custom HDL Code Using DocBlock

Integrate custom HDL code using the DocBlock block

Generate Black Box Interface for Subsystem

How to generate an interface to existing or legacy HDL code from a subsystem.

Generate Black Box Interface for Referenced Model

Specify a black box implementation for the Model block when you already have legacy or manually-written HDL code.

Specify Bidirectional Ports

Specify bidirectional ports for a black box

Generate Reusable Code for Atomic Subsystems

Generate shared code for identical subsystems or subsystems identical except for their mask parameter values

Customize Black Box or HDL Cosimulation Interface

How to use block implementation parameters to control generation and naming of ports and other attributes of the generated interface.

Third-Party Tools

Create an Altera DSP Builder Subsystem

Code generation from a model using both Altera DSP Builder and HDL Coder™.

Create a Xilinx System Generator Subsystem

Code generation from a model using both Xilinx System Generator for DSP and HDL Coder.

Generate a Cosimulation Model

Automatically generate a Simulink model that cosimulates with your HDL simulator.

Concepts

Pass-Through and No-Op Implementations

Bypassing or omitting selected subsystems in generated code.

Featured Examples