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Generate Black Box Interface for Subsystem

What Is a Black Box Interface?

A black box interface for a subsystem is a generated VHDL® component or Verilog® module that includes only the HDL input and output port definitions for the subsystem. By generating such a component, you can use a subsystem in your model to generate an interface to existing manually written HDL code, third-party IP, or other code generated by HDL Coder™.


  • The black box implementation is available only for subsystem blocks below the level of the DUT. Virtual and atomic subsystem blocks of custom libraries that are below the level of the DUT also work with black box implementations.

  • You can generate at most one clock port and one clock enable port for a black box subsystem. Therefore, the black box subsystem must be single-rate even if it is in a multirate DUT.

Generate a Black Box Interface for a Subsystem

To generate the interface, select the BlackBox implementation for one or more Subsystem blocks. Consider the following model that contains a subsystem top, which is the device under test.

The subsystem top contains two lower-level subsystems:

Suppose that you want to generate HDL code from top, with a black box interface from the Interface subsystem. To specify a black box interface:

  1. Right-click the Interface subsystem and select HDL Code > HDL Block Properties.

    The HDL Properties dialog box appears.

  2. Set Architecture to BlackBox.

    The following parameters are available for the black box implementation:

    The HDL block parameters available for the black box implementation enable you to customize the generated interface. See Customize Black Box or HDL Cosimulation Interface for information about these parameters.

  3. Change parameters as desired, and click Apply.

  4. Click OK to close the HDL Properties dialog box.

Generate Code for a Black Box Subsystem Implementation

When you generate code for the DUT in the ex_blackbox_subsys model, the following messages appear:

>> makehdl('ex_blackbox_subsys/top')
### Generating HDL for 'ex_blackbox_subsys/top'
### Starting HDL Check.
### HDL Check Complete with 0 errors, 0 warnings and 0 messages.

### Begin VHDL Code Generation
### Working on ex_blackbox_subsys/top/gencode as hdlsrc\gencode.vhd
### Working on ex_blackbox_subsys/top as hdlsrc\top.vhd
### HDL Code Generation Complete.

In the progress messages, observe that the gencode subsystem generates a separate file, gencode.vhd, for its VHDL entity definition. The Interface subsystem does not generate such a file. The interface code for this subsystem is in top.vhd, generated from ex_blackbox_subsys/top. The following code listing shows the component definition and instantiation generated for the Interface subsystem.

  COMPONENT Interface
    PORT( clk            :   IN    std_logic;
          clk_enable     :   IN    std_logic;
          reset          :   IN    std_logic;
          In1            :   IN    std_logic_vector(7 DOWNTO 0);  -- uint8
          In2            :   IN    std_logic_vector(15 DOWNTO 0);  -- uint16
          In3            :   IN    std_logic_vector(31 DOWNTO 0);  -- uint32
          Out1           :   OUT   std_logic_vector(31 DOWNTO 0)  -- uint32
  u_Interface : Interface
    PORT MAP( clk => clk,
              clk_enable => enb,
              reset => reset,
              In1 => gencode_out1,  -- uint8
              In2 => gencode_out2,  -- uint16
              In3 => gencode_out3,  -- uint32
              Out1 => Interface_out1  -- uint32

  enb <= clk_enable;

  ce_out <= enb;

  Out1 <= Interface_out1;

By default, the black box interface generated for subsystems includes clock, clock enable, and reset ports. Customize Black Box or HDL Cosimulation Interface describes how you can rename or suppress generation of these signals, and customize other aspects of the generated interface.

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