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Integrate Custom HDL Code Using DocBlock

You can use one or more DocBlock blocks to integrate custom HDL code into your design.

When To Use DocBlock to Integrate Custom Code

If you want to keep the HDL code with your model, instead of as a separate file, use a DocBlock to integrate custom HDL code. The text in the DocBlock is your custom VHDL® or Verilog® code.

You include each DocBlock that contains custom HDL code by placing it in a black box subsystem, and including the black box subsystem in your DUT. One HDL file is generated per black box subsystem.

Alternatives for Custom Code Integration

If you want to keep your custom HDL code separate from your model, such as when the custom code is IP or a library from a third party, use a black box subsystem or black box model reference.

How To Use DocBlock to Integrate Custom Code

  1. In your DUT, at any level of hierarchy, add a Subsystem block.

  2. For the Subsystem block, in the HDL Block Properties dialog box:

  3. In the subsystem, add a DocBlock block.

  4. For the DocBlock, in the HDL Block Properties dialog box:

    • Set Architecture to HDLText.

    • Set TargetLanguage to your target language, either Verilog or VHDL˙.

  5. In the DocBlock, enter the HDL code for your custom Verilog module or VHDL entity.

    The language must match the DocBlock TargetLanguage setting.

Restrictions

  • The black box subsystem that contains the DocBlock cannot be the top-level DUT.

  • You can have a maximum of two DocBlock blocks in the black box subsystem. If you have two DocBlock blocks, one must have TargetLanguage set to VHDL, and the other must have TargetLanguage set to Verilog.

    When generating code, HDL Coder™ only integrates the code from the DocBlock that matches the target language for code generation.

Example

The hdlcoderIncludeCustomHdlUsingDocBlockExample model shows how to integrate custom VHDL and Verilog code into your design with the DocBlock block.

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