BPSK Modulator Baseband

Modulate using BPSK method

• 

Libraries:
Communications Toolbox / Modulation / Digital Baseband Modulation / PM
Communications Toolbox HDL Support / Modulation / PM

Description

The BPSK Modulator Baseband block modulates a signal by using the binary phase shift keying (BPSK) method. The output is a baseband representation of the modulated signal. The input signal must be a discrete-time binary-valued signal. If the input bit is 0 or 1, then the modulated symbol is exp(jθ) or -exp(jθ), respectively. The Phase offset (rad) parameter specifies the value of θ in radians.

Examples

Cyclic Redundancy Check of Noisy BPSK Data Frames in Simulink

Use a CRC code to detect frame errors in a noisy BPSK signal.

Open Model

Frame Synchronization Using Barker Code Preamble

Use a length 13 Barker code frame preamble for frame synchronization of data bits.

Open Model

Ports

Input

In — Input data

scalar | vector

Input signal, specified as a scalar or vector with element values in the range [0,M – 1], where M is the modulation order. If you specify a binary vector, the number of elements must be an integer multiple of the number of bits per symbol. The number of bits per symbol is equal to log₂(M).

Data Types: single | double | int8 | int16 | int32 | uint8 | uint16 | uint32 | Boolean
Complex Number Support: Yes

Output

Out — BPSK-modulated baseband signal

scalar | vector

BPSK-modulated baseband signal, returned as a complex-valued scalar or vector.

Data Types: single | double | fixed point

Parameters

Main

Phase offset (rad) — Phase offset of zeroth point

0 (default) | scalar

Phase offset of the zeroth point of the constellation in radians, specified as a scalar.

Example: pi/4

Data Types

Output data type — Output data type

double (default) | single | Inherit via back propagation | fixdt(1,16) | fixdt(1,16,0) | <data type expression>

Output data type, specified as one of these options.

• double

• single

• Inherit via back propagation — The block matches the output data type and scaling to the next block in the model

• fixdt(1,16)

• fixdt(1,16,0)

• <data type expression> — Enables parameters for which you specify additional details

Block Characteristics

Data Types	Boolean | double | fixed pointa, b | integer | single
Multidimensional Signals	no
Variable-Size Signals	yes
a ufix(ceil(log2(M))) only at the input for M-ary modulation. b Fixed-point outputs must be signed.

More About

Constellation Visualization

Click View Constellation on the block mask to visualize a signal constellation for the specified block parameters. Parameter settings must be applied before viewing a constellation. For more information, see View Constellation of Modulator Block.

Algorithms

Phase modulation is a linear baseband modulation technique in which the message modulates the phase of a constant amplitude signal. Binary Phase Shift Keying (BPSK) is a two phase modulation scheme, where the 0’s and 1’s in a binary message are represented by two different phase states in the carrier signal

$$s_n(t)=\sqrt{\frac{2E_b}{T_b}}\cos \left(2\pi f_{c}t+{\varphi }_n\right),$$

for $$(n-1)T_b\le t\le n{T}_b,\text{ n}=\text{1},\text{2},\text{ 3},\dots$$where:

• ϕ_n = πm, m∈{0,1}.

• E_b is the energy per bit.

• T_b is the bit duration.

• f_c is the carrier frequency.

In MATLAB^®, the baseband representation of a BPSK signal is

$$s_n(t)=e^{-i{\varphi }_n}=\cos \left(\pi n\right).$$

The BPSK signal has two phases: 0 and π. The probability of a bit error in an AWGN channel is

$$P_b=Q\left(\sqrt{\frac{2E_b}{N_0}}\right),$$

where N₀ is the noise power spectral density.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate Verilog and VHDL code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Version History

Introduced before R2006a