A 2018 study revealed that 84% of FPGA design projects – including some safety-critical designs - suffered from non-trivial bugs escaping into production, with 10% having four or more bugs released into production.
In this webinar, MathWorks engineers will demonstrate a series of techniques that FPGA design teams in industry are using today to verify correct performance of FPGA designs using MATLAB and Simulink.
MathWorks engineers will demonstrate these techniques using example designs.
Mark Lin in an advance application engineer supporting ASIC/FPGA workflows who specializes in digital design verification. Mark was a verification engineer at Broadcom for eight years, where he developed full-chip test environments. He earned a BS degree in electrical engineering from California State University of Los Angeles.
Eric Cigan is the principal product marketing manager for ASIC and FPGA verification at MathWorks. Prior to joining MathWorks, he held technical marketing roles at MathStar, AccelChip, and Mentor Graphics. Eric earned BS and MS degrees in mechanical engineering from the Massachusetts Institute of Technology.
Recorded: 25 Aug 2020
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