From the series: Developing Radio Applications for RFSoC with MATLAB & Simulink
Eric Cigan, MathWorks
In the final video of the series, see how to use Simulink® models with SoC Blockset™ to perform code generation and deployment on hardware. To start, the Simulink model used in the previous video is augmented with a radar target simulation and a command interface for remotely controlling the radar algorithm over a UDP link to the host computer. Then see a demonstration of the radar algorithm running on the ZCU111 board, controlled by a MATLAB® script. An overview of the Simulink model for HDL and C code generation comes next, with more details on the command interface and how it interacts with the processor and FPGA, as well as the details on portions of the algorithm running on the FPGA.
Next comes the process of HDL and C code generation. The SoC Builder tool within SoC Blockset is used to configure code generation, including task mapping, configuring the memory map, validating the Simulink model, and launching C and HDL code generation.
You can then view the generated Vivado® project in Vivado IP Integrator, including the range-Doppler IP core, DMA cores, and RF data converter block.
Once the process of building the application and generating the bitstream is complete, the SoC Builder tool connects to the ZCU111, loads the design, reboots the board, and downloads the application to enable testing controlled from a MATLAB session.
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