How to update HDL verifier block when VHDL source changes its port definition?
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I couldn't find a way to update the block when vhdl source change its source file. So, I have to manually add or remove those definition after re compile the vhdl source. I wonder if this is the only way to do so.
Marc Erickson on 14 Nov 2022
You have cited two ways to update the interface: Re-running the cosimulation wizard or using the block mask "Ports" tab and using "New" or "Delete" buttons. A third way is the "Autofill" button on that same "Ports" tab.
If the update is small, the "New" / "Delete" method on the Ports tab should be preferred. Adding a new signal or removing an existing one will not affect the remaining current connections to the surrounding model blocks.
There is no way for the tool to know how to connect new ports. If the updates are expected (e.g. a set of debug ports will be added), you can script model updates with commands such as "add_block" and "add_line". See https://www.mathworks.com/help/simulink/programmatic-modeling.html for more infomation.
More Answers (1)
Kiran Kintali on 10 Nov 2022
Edited: Kiran Kintali on 11 Nov 2022
does your question refer to this workflow? Thanks
Cosimulation Type—Simulink Block
Open your model, and on the Apps tab, click HDL Verifier. Then, in the Mode section select HDL Cosimulation, and click Import HDL Files to open the Cosimulation Wizard.