DSP for FPGAs

This three-day course will review DSP fundamentals from the perspective of implementation within the FPGA fabric. Particular emphasis will be given to highlighting the cost, with respect to both resources and performance, associated with the implementation of various DSP techniques and algorithms.

Topics include:

• Introduction to FPGA hardware and technology for DSP applications
• DSP fixed-point arithmetic
• Signal flow graph techniques
• HDL code generation for FPGAs
• Fast Fourier Transform (FFT) Implementation
• Design and implementation of FIR, IIR and CIC filters
• CORDIC algorithm
• Design and implementation of adaptive algorithms such as LMS and QR algorithm
• Techniques for synchronisation and digital communications timing recovery

Day 1 of 3

Introduction to DSP FPGA Hardware

Objective: Provide introduction to DSP and FPGA. Understand general FPGA architecture and why FPGAs are uniquely suited to the implementation of DSP algorithms.

• From discrete logic to FPGAs -some history!
• The generic DSP system
• DSP cores and processors review
• Custom and semi-custom ASICs
• System-on-chip (SOC)
• FPGA flexibility and functionality
• FPGAs vs Programmable DSPs

FPGA Fundamental Concepts

Objective: Review the fundamental Concepts of FPGA-based implementations.

• Timing and critical path issues
• Pipelining
• Arithmetic implementation: multiply and add
• Parallel and serial implementations
• FIR Filters

FPGA Technology

Objective: Explore different AMD FPGA families and architectures. 

• The FPGA technology roadmap
• Clocking rates, data rates, and sample rates
• FPGA memory and registers
• Input/output blocks and requirements
• Bits, Slices, and Configurable Logic Blocks
• FPGA Families 

DSP Arithmetic Essentials

Objective: Understand fixed point binary arithmetic. Map arithmetic operations to AMD FPGA hardware.

• 2's complement fixed point arithmetic
• Full adders and multiplier cells
• Division and square root implementation
• Wordlength issues and Fixed point arithmetic
• Saturate and wraparound
• Overflow and underflow

Signal Flow Graph (SFG) Techniques

Objective: Review the representation of DSP algorithms using a signal flow graph. Use the Cut Set method to improve timing performance. Implement parallel and serial FIR filters.

• DSP/Digital Filter Signal Flow Graphs
• Latency, delays, and "anti-delays"
• Re-timing: Cut-set and delay scaling
• The transpose FIR
• Pipelining and multichannel architectures
• SFG topologies for FPGAs

Digital Filtering

Objective: Explore the different filter topologies

• Low pass, high pass, band pass, and band stop
• FIR, IIR, Adaptive
• Impulse Response
• Frequency Response

Day 2 of 3

Recursive DSP Retiming (IIR and LMS)

Objective: Review the retiming of parallel DSP signal flow graph architectures with feedback loops

• IIR
• Adaptive LMS
• Non-Canonical LMS

Serial Filter Implementation

Objective: Explore efficient implementation of oversampledfilters.

• Serial filters
• Serial-parallel filters
• Hardware cost

Multi-Channel Filter Implementation

Objective: Develop multi-channel filters using time-sharing signal flow graphs

• Cut set retiming
• Delay scaling rule
• Implementation issues
• Extending serial filters to multiple channels

Frequency Domain Processing

Objective: Discuss the theory and FPGA implementation of the Fast Fourier Transform.

• DFT, FFT and IFFT
• FFT FPGA architectures
• FFT wordlength growth and accuracy

Multirate Signal Processing for FPGAs

Objective: Develop polyphase structure for efficient implementation of multirate filters. Use CIC filter for interpolation and decimation.

• Upsampling and interpolation filters
• Downsampling and decimation filters
• Efficient arithmetic for FIR implementation
• Integrators and differentiators
• Half-band, moving average and comb filters
• Cascade Integrator Comb (CIC) Filters (Hogenauer)
• Efficient arithmetic for IIR Filtering

Day 3 of 3

CORDIC Techniques

Objective: Introduce the CORDIC algorithm for calculating trigonometric, linear,  and hyperbolic functions.

• CORDIC rotation mode and vector mode
• Compute cosine and sine function
• Compute vector magnitude and angle
• Architecture for FPGA implementation

Adaptive DSP Algorithms and Applications

Objective: Introduce the LMS algorithm in adaptive signal processing. Illustrate QR algorithm as a Recursive Least Squares (RLS) technique and why it suits FPGA implementation.

• Adaptive applications (equalization, beamforming)
• LMS Algorithms and parallel implementation
• Non-canonical LMS algorithms
• Linear algebra; solving linear systems of equations
• The QR algorithm for adaptive signal processing
• QR processing requirements and numerical issues

Numerically Controlled Oscillators

Objective: Learn and compare different NCO architectures

• IIR filters
• CORDIC rotations
• Lookup Tables
• Evaluate spectral purity and SFDR

Timing and Synchronization Issues

Objective: Discuss symbol timing recovery, carrier phase recovery, carrier frequency recovery, and frame synchronization.

• Carrier recovery, squaring and Costas loops, PLLs
• Phase rotations; Sampling rate conversions
• Symbol timing recovery, early/late gate detection
• Delay locked loop timing and synchronization