Generating HDL Code from Simulink

Day 1 of 2

Preparing Simulink Models for HDL Code Generation

Objective: Prepare a Simulink model for HDL code generation. Generate HDL code and testbench for simple models that require no optimization.

• Preparing Simulink models for HDL code generation
• Generating HDL code
• Generating a test bench
• Verifying generated HDL code with an HDL simulator

Fixed-Point Precision Control

Objective: Establish correspondence between generated HDL code and specific Simulink blocks in the model. Use the Fixed-Point Tool to finalize the model's fixed-point architecture.

• Fixed-point scaling and inheritance
• Fixed-Point Designer workflow
• Fixed-Point Tool
• Command-line interface

Generating HDL Code for Multirate Models

Objective: Generate HDL code for multirate designs. Understand different modeling strategies to implement multirate designs.

• Preparing a multirate model for generating HDL code
• Generating HDL code with single or multiple clock pins
• Verifying multirate designs with co-simulation
• Designing a simplified streaming interface for multirate applications

Day 2 of 2

Optimizing Generated HDL Code

Objective: Use pipelines to meet design timing requirements. Use specific hardware implementations and share resources to optimize the area.

• Generating HDL code with the HDL Workflow Advisor
• Meeting timing requirements via pipelining
• Choosing specific hardware implementations for compatible Simulink blocks
• Sharing FPGA/ASIC resources in subsystems
• Verifying that the optimized HDL code is bit-true cycle-accurate
• Mapping Simulink blocks to dedicated hardware resources on the FPGA

Modeling and Optimizing Streaming Architectures

Objective: Model hardware-friendly streaming architectures using explicit control signals. Include timing and area optimizations manually and ensure backpressure propagation.

• Model a fully parallel streaming architecture
• Insert pipeline registers into a clock rate model
• Understand the modeling steps from a parallel to serial architecture
• Ensure correct stall behavior with valid/ready handshaking

Using Native Floating Point

Objective: Implement floating-point values and operations in your HDL code.

• Why and when to use native floating-point
• Target-independent HDL code generation with HDL Coder
• Fixed-point vs. floating-point comparison
• Optimization of floating-point implementations

Interfacing External HDL Code with Generated HDL

Objective: Incorporate existing HDL code in your design using the blackbox interface. Parameterize HDL code to increase reusability and readability.

• Interfacing external HDL code
• Increase code reusability and readability