NR Polar Encoder
Libraries:
Wireless HDL Toolbox /
Error Detection and Correction
Description
The NR Polar Encoder block implements a streaming polar encoder with hardware-friendly control signals. The 5G NR standard requires polar encoding for channel coding of the DCI, UCI, and BCH transmit channels.
The encoder implementation matches the nrPolarEncode
(5G Toolbox) function.
You must specify the link direction because the coding scheme defined by the 5G NR standard is different for downlink and uplink messages. Downlink messages are encoded with interleaving and uplink messages do not use interleaving.
Because the latency of this operation can vary, the block provides an output signal, nextFrame, that indicates when the block is ready to accept new inputs. For more details, see the Latency section on this page.
Examples
Polar Encode and Decode of Streaming Samples
Simulate NR Polar Encode and Decode blocks and compare the hardware-optimized results with results from 5G Toolbox™ functions.
Ports
Input
data — Input data bit
scalar
Input data bit, specified as a scalar.
The software supports double
and
single
data types for simulation, but not for HDL code generation.
Data Types: fixdt(0,1,0)
| Boolean
| double
| single
ctrl — Control signals accompanying sample stream
samplecontrol
bus
Control signals accompanying the sample stream, specified as a
samplecontrol
bus. The bus includes the start
,
end
, and valid
control signals, which indicate the
boundaries of the frame and the validity of the samples.
start
— Indicates the start of the input frameend
— Indicates the end of the input framevalid
— Indicates that the data on the input data port is valid
For more details, see Sample Control Bus.
Data Types: bus
K — Length of information block in bits
positive integer
Length of information block in bits, specified as a positive integer. For downlink messages, K must be in the range 36 to 164. For uplink messages, K must be in the range 18 to 25 or 31 to 1023.
Dependencies
To enable this port, set the Configuration source parameter
to Input port
.
Data Types: fixdt(0,10,0)
E — Rate-matched output length in bits
positive integer
Rate-matched output length in bits, specified as a positive integer. Specify a value for E that is greater than K and less than or equal to 8192.
Dependencies
To enable this port, set the Configuration source parameter
to Input port
.
Data Types: fixdt(0,14,0)
Output
data — Encoded data bit
scalar
Encoded data bit, returned as a scalar. The block returns a message of
N sequential bits. N is a power of two
determined from the values of K and E. The
maximum output message size is 512 bits when the Link direction
is Downlink
and 1024 bits when the Link
direction is Uplink
.
Data Types: fixdt(0,1,0)
| Boolean
| double
| single
ctrl — Control signals accompanying sample stream
samplecontrol
bus
Control signals accompanying the sample stream, returned as a samplecontrol
bus. The bus includes the start
, end
, and
valid
control signals, which indicate the boundaries of the frame
and the validity of the samples.
start
— Indicates the start of the output frameend
— Indicates the end of the output framevalid
— Indicates that the data on the output data port is valid
For more details, see Sample Control Bus.
Data Types: bus
nextFrame — Ready for new inputs
scalar
The block sets this signal to 1
when the block is ready to accept the start
of the next frame. If the block receives an input start signal
while nextFrame is 0
, the block discards the
frame in progress and begins processing the new data.
For more information, see Using the nextFrame Output Signal.
Data Types: Boolean
Parameters
Link direction — Direction of 5G NR link
Downlink
(default) | Uplink
When you select Downlink
, the block performs
interleaving, as specified in the 5G NR standard. When you select
Uplink
, the block omits the interleaving logic.
Configuration source — Source for K and E
Property
(default) | Input port
Select Input port
to enable the K
and E ports. Select Property
to use the
Message length (K) and Rate-matched length
(E) parameters.
Message length (K) — Length of information block in bits
56
(default) | positive integer
For downlink messages, K must be in the range 36 to 164. For uplink messages, K must be in the range 18 to 25 or 31 to 1023.
Dependencies
To enable this parameter, set the Configuration source
parameter to Property
.
Rate-matched length (E) — Rate-matched output length in bits
864
(default) | positive integer
Specify a value for E that is greater than K and less than or equal to 8192.
Dependencies
To enable this parameter, set the Configuration source
parameter to Property
.
Tips
You cannot use this block inside an Enabled Subsystem or Resettable Subsystem.
Algorithms
This block implements the encoder by using
log2(N)
parallel encoding
stages. The block stores the whole message in the buffer, then interleaves and maps the
information bits based on the pattern specified in the standard for the values of
K and E. The interleaving step is included only
when you set the Link direction parameter to
Downlink
.
This diagram shows the architecture of the polar encoder.
The block uses the Configuration stage when the input K and
E values change. The block computes the new message length,
N, and the locations of the information bits, then passes them to the
buffer and the mapping stage. Because the mapping patterns are computed as needed, rather than
stored in hardware, the block supports all K and E
values within the supported range. The Configuration stage also computes the interleave
pattern when you set the Link direction parameter to
Downlink
.
When you set the Configuration source parameter to
Property
, the K and E
values are constants, so the decoder does not implement the Configuration stage. In this case,
the block includes static lookup tables that contain the precomputed configuration.
Latency
The exact latency varies based on the values of K and E. The latency is longer for frames where the K and E values change and the block must compute the new configuration. Because the latency varies, use the output nextFrame control signal to determine when the block is ready for a new input frame.
This waveform shows how the latency varies with values of K and E. For the first frame with a given K and E value, the block must determine the message length and information bit mapping for those values. This configuration step means that the block takes longer to start returning the encoded samples. In this case, the block also takes longer before it is ready to accept the next input frame. When the input K and E values are 132 and 256, respectively, the block has a latency of 535 cycles from the input start signal to the output nextFrame. For subsequent frames with the same values for K and E, the block is ready sooner because it does not need to recompute the configuration. The waveform shows this new latency is 389 cycles. When the K and E values change to 54 and 124, respectively, the block must compute the new configuration and the latency changes to 443 cycles.
Performance
This table shows the resource and performance data synthesis results of the block when
it is configured with K and E as input ports and
the Link direction parameter set to Uplink
.
The generated HDL is targeted to an AMD®
Zynq®-7000 ZC706 evaluation board. The design achieves a clock frequency of 450
MHz.
Resource | Number Used |
---|---|
Slice LUTs | 637 |
Slice Registers | 934 |
Block RAM | 2.5 |
This table shows the resource and performance data synthesis results of the block when
it is configured with K and E as input ports and
the Link direction parameter set to
Downlink
. The generated HDL is targeted to a AMD
Zynq-7000 ZC706 evaluation board. The design achieves a clock frequency of 450
MHz.
Resource | Number Used |
---|---|
Slice LUTs | 600 |
Slice Registers | 948 |
Block RAM | 3.5 |
The block uses fewer resources when K and E are specified by parameters.
References
[1] 3GPP TS 38.212. "NR; Physical channels and modulation." 3rd Generation Partnership Project; Technical Specification Group Radio Access Network. URL: https://www.3gpp.org.
[2] Arikan, Erdal. "Channel Polarization: A Method for Constructing Capacity-Achieving Codes for Symmetric Binary-Input Memoryless Channels." IEEE Transactions on Information Theory 55, no. 7 (July 2009): 3051–73. https://doi.org/10.1109/TIT.2009.2021379.
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
This block supports C/C++ code generation for Simulink® accelerator and rapid accelerator modes and for DPI component generation.
HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has one default HDL architecture.
ConstrainedOutputPipeline | Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is
|
InputPipeline | Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
OutputPipeline | Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is
|
You cannot generate HDL for this block inside a Resettable Synchronous Subsystem (HDL Coder).
Version History
Introduced in R2020a
See Also
nrPolarEncode
(5G Toolbox) | NR Polar Decoder
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