Implement on Hardware
You can design an SDR algorithm in Simulink®, and then prototype your design on the AMD Zynq-based radio hardware. You can either deploy a hardware-software (HW/SW) co-design implementation partitioned between the ARM® processor and the FPGA fabric of the underlying system on chip (SoC), or prototype the design targeting the FPGA fabric only. The workflow is available in Simulink only.
Functions
sdrdev | Create radio object for interfacing with Xilinx Zynq-based radio hardware |
downloadImage | Download SD card image or bitstream file |
Objects
comm.SDRDevAD936x | Interface with AD936x-based Zynq radio hardware |
comm.SDRDevFMCOMMS5 | Interface with FMCOMMS5 Zynq radio hardware |
Blocks
| AD936x Transmitter | Send data to AD936x-based Zynq radio hardware (Since R2024b) |
| AD936x Receiver | Receive data from AD936x-based Zynq radio hardware (Since R2024b) |
| FMCOMMS5 Transmitter | Send data to FMCOMMS5 Zynq radio hardware |
| FMCOMMS5 Receiver | Receive data from FMCOMMS5 Zynq radio hardware |
Topics
- Hardware-Software Co-Design Overview
Learn the basics of the hardware-software co-design feature in this support package and its software requirements.
- Installation for Hardware-Software Co-Design
Install and configure additional support packages and third-party tools required by hardware-software co-design workflow.
- Hardware-Software Co-Design Workflow
Deploy partitioned hardware-software co-design implementations for SDR algorithms.
- Guidelines for Configuring the Software Interface Model
Configure your model for continuous and packet-based transmission and reception.
- System Timing
Explore ARM processor scheduler options for the software interface model.
- FPGA Targeting Workflow
Prototype SDR algorithms on the FPGA fabric only.
Troubleshooting
Troubleshooting Hardware-Software Co-Design
Resolve issues encountered while using the hardware-software co-design workflow.
Featured Examples
5G NR MIB Recovery Using Analog Devices AD9361/AD9364
Deploy a hardware-software co-design implementation of a MIB recovery algorithm for off-the-air 5G NR waveforms.
5G NR SIB1 Recovery Using Analog Devices AD9361/AD9364
Deploy a hardware-software co-design implementation of a SIB1 recovery algorithm for off-the-air 5G NR waveforms.
HW/SW Co-Design with AXI4-Stream Using Analog Devices AD9361/AD9364
Deploy a hardware-software co-design implementation of a waveform transmitter and receiver using AXI4-Stream.
OFDM Transmit and Receive Using Analog Devices AD9361/AD9364
Deploy a hardware-software co-design implementation of an OFDM-based transmit and receive algorithm.
Verify OFDM Transmit and Receive using FPGA Data Capture
Debug, visualize, and analyze the internal signals of a wireless HDL IP while you run the complete design on hardware.
DVB-S2 HDL PL Header Recovery Using Analog Devices AD9361/AD9364
Deploy a hardware-software co-design implementation of a DVB-S2 HDL PL header recovery algorithm.
WLAN Receiver Using Analog Devices AD9361/AD9364
Deploy a hardware-software co-design implementation of a WLAN HDL receiver system to recover information from a WLAN signal.
HW/SW Co-Design QPSK Transmit and Receive Using Analog Devices AD9361/AD9364
Implement QPSK transmitter and receiver algorithm partitioned across the ARM and the FPGA fabric.
HW/SW Co-Design Implementation of ADS-B Receiver Using Analog Devices AD9361/AD9364
Partition ADS-B receive functionality across the ARM and the FPGA fabric.
LTE MIB Recovery and Cell Scanner Using Analog Devices AD9361/AD9364
Implement an LTE MIB recovery system partitioned across the ARM and the FPGA fabric and detect LTE cell signals in the vicinity.
LTE SIB1 Recovery Using Analog Devices AD9361/AD9364
Recover the first system information block (SIB1) from an LTE downlink signal using ARM and FPGA resources.
Deploy and Verify HDL Neural Network Based DPD on FPGA
Deploy neural-network-based digital predistorter (NN DPD) algorithm and verify using OFDM signal.
Deploy and Verify Modulation Classification on RFSoC Devices
Deploy pretrained CNN for modulation classification on AMD RFSoC device.
