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status = sldvrun analyzes the current model to generate the test cases that provide the model coverage or prove the model properties.

status = sldvrun(model) analyzes model to generate the test cases that provide the model coverage or prove the model properties

status = sldvrun(subsystem) converts the atomic subsystem subsystem into a new model and runs a design verification analysis on the new model.


status = sldvrun(model, options) analyzes model by using the sldvoptions object options.

[status, filenames] = sldvrun(model, options) analyzes model and returns the filenames that the software creates during the analysis.

[status, filenames] = sldvrun(model, options, showUI, startCov) opens the log window during the analysis if you set showUI to true. If you set showUI to false (the default), sldvrun directs output to the MATLAB® command line.


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Set sldvoptions parameters and analyze the model by using the specified options

Set sldvoptions parameters:

opts = sldvoptions;
opts.Mode = 'TestGeneration';              % Perform test-generation analysis
opts.ModelCoverageObjectives = 'MCDC';     % MCDC coverage
opts.SaveHarnessModel = 'off';             % Don't save harness as model file
opts.SaveReport = 'on';                    % Save the HTML report

Open the sldvdemo_cruise_control model and analyze the model by using the specified options:

open_system ('sldvdemo_cruise_control');
[ status, files ] = sldvrun('sldvdemo_cruise_control', opts);

Input Arguments

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Handle to a Simulink® model.

Handle to an atomic subsystem in a Simulink model.

sldvoptions object that specifies the analysis options.

Logical value indicating where to display the messages during the analysis:

true to display the messages in the log window.
false (default) to display the messages in the Command Window.

cvdata object that specifies the model coverage objects for the software to ignore.

Output Arguments

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A structure whose fields list the file names that the Simulink Design Verifier™ software generates.


MAT-file with raw input data


Simulink harness model


HTML report of the simulation results


Simulink model extracted from subsystem


Simulink model obtained after block replacements

These values that list the status of the analysis.


Analysis exceeded the maximum processing time




Processing completed normally


To run an analysis with Simulink Design Verifier, on the Design Verifier tab, in the Mode section, select any of these options:

  • Select Design Error Detection, then click Detect Design Errors.

  • Select Test Generation, then click Generate Tests.

  • Select Property Proving, then click Prove Properties.

Introduced in R2007a