Detect and Address Logical Errors

Identify logical errors in your model by using dead logic detection

Identify logical errors where coverage conditions cannot satisfy all expected values by using dead logic detection.

Topics

Dead Logic Detection
Describes the two analysis modes for dead logic detection in Simulink^® Design Verifier™.
Common Causes for Dead Logic
Describes several scenarios that results in dead logic.
Detect Dead Logic Caused by an Incorrect Value
Example showing how to find an incorrect input specification using a dead logic result.
Check for Specified Minimum and Maximum Value Violations
Describes how to analyze the model to verify that specified design minimum and maximum values are honored.
Analyze Models for Design Errors
Run a Design Error Detection Analysis and interpret the results.

Featured Examples

Analyzing the Results for a Dead Logic Analysis

Demonstrates how to isolate potential causes of dead logic using the sldvexCommonCausesOfDeadLogic model. Dead logic detection finds unreachable objectives in the model that cause the model element to remain inactive.

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Debug Enhanced Modified Condition Decision Coverage Using Model Slicer

Find the Simulink Design Verifier generated objectives related to a specific model object using Model Slicer.

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