Get Started with HDL Verifier
HDL Verifier™ lets you test and verify VHDL® and Verilog® designs for FPGAs, ASICs, and SoCs. You can verify RTL with testbenches running in MATLAB® or Simulink® using cosimulation with Siemens® Questa® or ModelSim®, Cadence® Xcelium™, and the Xilinx® Vivado® simulator. You can reuse these same testbenches with FPGA development boards to verify hardware implementations.
HDL Verifier generates SystemVerilog verification models for RTL testbenches and complete Universal Verification Methodology (UVM) environments. These models run natively in the Questa, Xcelium, and Vivado simulators, as well as Synopsys® VCS via the SystemVerilog Direct Programming Interface (DPI).
HDL Verifier provides tools for debugging and testing implementations on Xilinx, Intel®, and Microchip boards from MATLAB. You can insert probes into designs and set trigger conditions to upload internal signals into MATLAB for visualization and analysis.
- Verify HDL Module with MATLAB Test Bench
This tutorial guides you through the basic steps to set up an HDL Verifier™ application that uses MATLAB® to verify a simple HDL design.
- Verify HDL Module with Simulink Test Bench
Set up an HDL Verifier session that uses Simulink to verify a simple VHDL model.
- Get Started with TLM Generator
This example shows how to configure a Simulink® model to generate a SystemC™/TLM component using the tlmgenerator target for either Simulink Coder™ or Embedded Coder®.
- Verify HDL Implementation of PID Controller Using FPGA-in-the-Loop
This example shows you how to set up an FPGA-in-the-Loop (FIL) application using HDL Verifier™.
- Verify Digital Up-Converter Using FPGA-in-the-Loop
This example shows you how to verify a digital up-converter design generated with Filter Design HDL Coder™ using FPGA-in-the-Loop simulation.
- Choose a Test Bench for Generated HDL Code (HDL Coder)
Select a generated test bench.
- Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor (HDL Coder)
Generate test bench and code coverage for generated HDL code using the HDL Workflow Advisor.
HDL Code Import
TLM Component Generation
Verify Generated HDL Code with HDL Workflow Advisor (requires HDL Coder license)
Design Verification Automation
- HDL Cosimulation
The HDL Verifier software consists of MATLAB functions, a MATLAB System object™, and a library of Simulink blocks, all of which establish communication links between the HDL simulator and MATLAB or Simulink.
- FPGA Verification
HDL Verifier works with Simulink or MATLAB and HDL Coder™ and the supported FPGA development environment to prepare your automatically generated HDL code for implementation in an FPGA.
- TLM Component Generation
HDL Verifier lets you create a SystemC Transaction Level Model (TLM) that can be executed in any OSCI-compatible TLM 2.0 environment, including a commercial virtual platform.
- SystemVerilog DPI Component Generation
HDL Verifier works with Simulink Coder™ or MATLAB Coder to export a subsystem as generated C code inside a SystemVerilog component with a Direct Programming Interface (DPI).
HDL Verifier Overview
Test and verify Verilog and VHDL designs for FPGAs, ASICs, and SoCs with HDL Verifier. Verify RTL with testbenches running in MATLAB or Simulink using cosimulation with HDL simulators. Use these same testbenches with FPGA and SoC development boards to verify HDL implementations in hardware.