Guidelines for Supported Blocks and Data Types - By Numbered List
The HDL modeling guidelines are a set of recommended guidelines that you can follow when creating Simulink® model for code generation with HDL Coder™. The guidelines for supported blocks and data types consist of guidelines for using various blocks in the HDL Coder block library, and about the supported data types. Each modeling guideline for HDL code generation has a different level of severity that indicates the levels of compliance requirements. To learn more about these severity levels, see HDL Modeling Guidelines Severity Levels.
These tables list the guidelines for supported data types in HDL Coder and for various blocks in the HDL Coder block library. The guidelines
start from 2.1
and are divided into subsections. In the table, you
see that certain guidelines have an associated model check. You can follow the modeling
pattern recommended for these guidelines by running that check in the HDL Code Advisor.
To learn more about the HDL Code Advisor, see Check HDL Compatibility of Simulink Model Using HDL Code Advisor.
Guidelines 2.1: HDL RAMs and HDL Operations Library
Guideline ID | Title | Severity | Associated Model Check/Coding Standard Rule |
---|---|---|---|
2.1.1 | RAM Block Access Considerations | Recommended | None |
2.1.2 | Serial to Parallel Conversion | Recommended | None |
Guidelines 2.2: Logic and Bit Operations Library
Guideline ID | Title | Severity | Associated Model Check/Coding Standard Rule |
---|---|---|---|
2.2.1 | Logical and Arithmetic Bit Shift Operations | Informative | None |
2.2.2 | Usage of Logical Operator, Bitwise Operator, and Bit Reduce Blocks | Informative | None |
2.2.3 | Use Boolean Output for Compare to Constant and Relational Operator Blocks | Strongly Recommended | None |
Guidelines 2.3: Lookup Table and Signal Routing Blocks
Guideline ID | Title | Severity | Associated Model Check/Coding Standard Rule |
---|---|---|---|
2.3.1 | Generate FPGA Block RAM from Lookup Tables | Strongly Recommended | None |
2.3.2 | Recommended Block Parameter Settings of Multiport Switch Block for Numeric and Enumerated Types | Recommended | None |
2.3.3 | Guidelines for Using Selector Blocks to Extract Input Elements from Vector or Matrix Signals | Recommended | None |
2.3.4 | Guidelines for Using Assignment Blocks to Write Elements in Vectors, Matrices, and 3-D Arrays | Recommended | None |
Guidelines 2.4: Ports and Subsystems
Guideline ID | Title | Severity | Associated Model Check/Coding Standard Rule |
---|---|---|---|
2.4.1 | Virtual Subsystem: Use as DUT | Mandatory | Model Check: Check for invalid top level subsystem |
2.4.2 | Atomic and Virtual Subsystems: Generate Reusable HDL Files | Recommended | None |
2.4.3 | Variant Subsystem: Using Variant Subsystems for HDL Code Generation | Mandatory | None |
2.4.4 | Model References: Build Model Design Using Smaller Partitions | Recommended | None |
2.4.5 | Block Settings of Enabled and Triggered Subsystems | Mandatory | None |
Guideline 2.5: Rate Change and Constant Blocks
Guideline ID | Title | Severity | Associated Model Check/Coding Standard Rule |
---|---|---|---|
2.5.1 | Usage of Rate Conversion Blocks | Recommended | None |
2.5.2 | Use Discrete and Finite Sample Time for Constant Block | Recommended | Model Check: Check for infinite and continuous sample time sources |
2.5.3 | Dynamically Change Sample Offset for Downsample Block | Informative | None |
Guideline 2.6: Delay Blocks
Guideline ID | Title | Severity | Associated Model Check/Coding Standard Rule |
---|---|---|---|
2.6.1 | Appropriate Usage of Delay Blocks as Registers | Recommended | Check for obsolete Unit Delay Enabled/Resettable Blocks |
2.6.2 | Absorb Delays to Avoid Timing Difference | Recommended | None |
2.6.3 | Map Large Delays to Block RAM | Recommended | None |
2.6.4 | Required HDL Settings for Goto and From Blocks | Mandatory | None |
Guideline 2.7: Multiplication and Accumulation Operations
Guideline ID | Title | Severity | Associated Model Check/Coding Standard Rule |
---|---|---|---|
2.7.1 | Designing Multipliers and Adders for Efficient Mapping to DSP Blocks on FPGA | Strongly Recommended | None |
2.7.2 | Set ConstMultiplierOptimization HDL Block Property to auto for Gain Block | Recommended | None |
2.7.3 | Use ShiftAdd Architecture of Divide Block for Fixed-Point Types | Recommended | None |
2.7.4 | Use Gain Block for Fixed-Point Constant Operations | Strongly Recommended | None |
Guideline 2.8: MATLAB Function Blocks
Guideline ID | Title | Severity | Associated Model Check/Coding Standard Rule |
---|---|---|---|
2.8.1 | Update Persistent Variables at End of MATLAB Function | Strongly Recommended | None |
2.8.2 | Avoid Algebraic Loop Errors from Persistent Variables inside MATLAB Function Blocks | Mandatory | None |
2.8.3 | Use hdlfimath Setting and Specify fi Objects inside MATLAB Function Block | Strongly Recommended | Check for MATLAB Function block settings |
Guideline 2.9: Stateflow Charts
Guideline ID | Title | Severity | Associated Model Check/Coding Standard Rule |
---|---|---|---|
2.9.1 | Choose State Machine Type based on HDL Implementation Requirements | Strongly Recommended | None |
2.9.2 | Specify Block Configuration Settings of Stateflow Chart | Strongly Recommended | Check for Stateflow chart settings |
2.9.3 | Data Type Settings and Casting in Stateflow Chart for HDL Code Generation | Informative | None |
2.9.4 | Using Absolute Time Temporal Logic in Stateflow Charts | Mandatory | None |
2.9.5 | Modeling Error (default) State in Stateflow Charts | Informative | None |
2.9.6 | Enable Clock-Driven Outputs of Stateflow Charts (Moore Charts Only) | Informative | None |
2.9.7 | Enumeration type for active state monitoring in a Stateflow chart with no default value | Informative | None |
Guidelines 2.10: Data Types
Guideline ID | Title | Severity | Associated Model Check/Coding Standard Rule |
---|---|---|---|
2.10.1 | Use Boolean for Logical Data and Ufix1 for Numerical Data | Mandatory | None |
2.10.2 | Specify Data Type of Gain Blocks | Recommended | None |
2.10.3 | Enumerated Data Type Restrictions | Mandatory | None |
2.10.4 | Choose Optimal Simulink Block to Compute Sine and Cosine Functions with Fixed-Point Data Types | Recommended | None |
2.10.5 | Choose Optimal Simulink Block to Compute Sine and Cosine Functions with Floating-Point Data Types | Recommended | None |
2.10.6 | Guidelines for Using Rounding and Saturation Settings for Fixed-Point Data Types | Recommended | None |
Guidelines 2.11: Square Root Operations
Guideline ID | Title | Severity | Associated Model Check/Coding Standard Rule |
---|---|---|---|
2.11.1 | Use SqrtFunction Architecture for Square Root Block | Recommended | None |