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FPGA Data Capture

Capture data to MATLAB or Simulink from RFSoC devices

Capture raw data using FPGA input and output (IO) application programming interface (API) from the Xilinx® Zynq® UltraScale+™ ZCU111 evaluation kit or Xilinx Zynq UltraScale+ ZCU216 evaluation kit. Configure an SoC model for the HDL code generation by using the HDL Workflow Advisor. Generate the HDL code for your algorithm, build and deploy the HDL design on an RFSoC device, and run a MATLAB® script to interactively capture data from the deployed HDL design.



Zynq RFSoC Template BuilderGenerate template model based on selected RFSoC reference design (Since R2021a)