Get Started with Deep Learning HDL Toolbox

Deep Learning HDL Toolbox™ provides functions and tools to prototype and implement deep learning networks on FPGAs and SoCs. It provides pre-built bitstreams for running a variety of deep learning networks on supported Xilinx^® and Intel^® FPGA and SoC devices. Profiling and estimation tools let you customize a deep learning network by exploring design, performance, and resource utilization tradeoffs.

Deep Learning HDL Toolbox enables you to customize the hardware implementation of your deep learning network and generate portable, synthesizable Verilog^® and VHDL^® code for deployment on any FPGA or SoC (with HDL Coder™ and Simulink^®).

Tutorials

• Supported Networks, Layers, Boards, and Tools
  

  Pretrained deep learning networks and network layers for which code can be generated by Deep Learning HDL Toolbox.

• Try Deep Learning on FPGA with Only Five Additional Lines of MATLAB Code
  

  Use Deep Learning HDL Toolbox to identify objects on a live webcam with the ResNet-18 pretrained network which has been deployed to a FPGA or SoC board.

• Configure Command-Line Session for Intel SoC Device
  

  Open a serial command-line session with Intel SoC device.

• Troubleshoot Xilinx Zynq Platform and Development Computer Connection
  

  To determine if the Xilinx Zynq^® platform is properly configured, repeat the steps in TFTP/WFTPD Configuration Guide.

• Deep Learning on FPGA Solution
  

  Rapidly prototype custom deep learning networks on FPGA by leveraging the deep learning on FPGA solution.

Featured Examples

Get Started with Deep Learning FPGA Deployment on Intel Arria 10 SoC

Create, compile, and deploy a dlhdl.Workflow object that has a handwritten character detection series network object by using the Deep Learning HDL Toolbox™ Support Package for Intel FPGA and SoC. Use MATLAB® to retrieve the prediction results from the target device.

• Open Live Script

Get Started with Deep Learning FPGA Deployment on Xilinx ZCU102 SoC

Create, compile, and deploy a dlhdl.Workflow object that has a handwritten character detection network as the network object by using the Deep Learning HDL Toolbox™ Support Package for Xilinx FPGA and SoC. Use MATLAB® to retrieve the prediction results from the target device.

• Open Live Script

Get Started with Deep Learning FPGA Deployment on Xilinx ZC706 SoC

Create, compile, and deploy a handwritten character detection series network to an FPGA and use MATLAB® to retrieve the prediction results.

• Open Live Script

Profile Network to Determine Performance Bottlenecks

Identify performance bottlenecks in a deep learning network on an FPGA by using the Profile option of the predict method.

• Open Live Script

Accelerate Prototyping Workflow for Large Networks by Using Ethernet

Deploy a deep learning network and obtain prediction results using the Ethernet connection to your target device. You can significantly speed up the deployment and prediction times for large deep learning networks by using Ethernet versus JTAG. This example shows the workflow on a ZCU102 SoC board. The example also works on the other boards supported by Deep Learning HDL Toolbox. See Deep Learning HDL Toolbox Supported Hardware.

• Open Live Script