This example shows how to create, compile, and deploy a
dlhdl.Workflow object that has a handwritten character detection series network object by using the Deep Learning HDL Toolbox™ Support Package for Intel FPGA and SoC. Use MATLAB® to retrieve the prediction results from the target device.
Intel Arria™ 10 SoC development kit
Deep Learning HDL Toolbox™ Support Package for Intel FPGA and SoC
Deep Learning HDL Toolbox™
Deep Learning Toolbox™
To load the pretrained series network, that has been trained on the Modified National Institute Standards of Technology (MNIST) database, enter:
snet = getDigitsNetwork();
To view the layers of the pretrained series network, enter:
Create a target object that has a custom name for your target device and an interface to connect your target device to the host computer. Interface options are JTAG and Ethernet. To use JTAG, install Intel™ Quartus™ Prime Standard Edition 18.1. Set up the path to your installed Intel Quartus Prime executable if it is not already set up. For example, to set the toolpath, enter:
% hdlsetuptoolpath('ToolName', 'Altera Quartus II','ToolPath', 'C:\altera\18.1\quartus\bin64');
hTarget = dlhdl.Target('Intel')
hTarget = Target with properties: Vendor: 'Intel' Interface: JTAG
Create an object of the
dlhdl.Workflow class. When you create the object, specify the network and the bitstream name. Specify the saved pretrained MNIST neural network, snet, as the network. Make sure that the bitstream name matches the data type and the FPGA board that you are targeting. In this example, the target FPGA board is the Intel Arria 10 SOC board and the bitstream uses a single data type.
hW = dlhdl.Workflow('network', snet, 'Bitstream', 'arria10soc_single','Target',hTarget)
hW = Workflow with properties: Network: [1×1 SeriesNetwork] Bitstream: 'arria10soc_single' ProcessorConfig:  Target: [1×1 dlhdl.Target]
To compile the MNIST series network, run the compile function of the
dn = hW.compile;
### Optimizing series network: Fused 'nnet.cnn.layer.BatchNormalizationLayer' into 'nnet.cnn.layer.Convolution2DLayer' offset_name offset_address allocated_space _______________________ ______________ ________________ "InputDataOffset" "0x00000000" "4.0 MB" "OutputResultOffset" "0x00400000" "4.0 MB" "SystemBufferOffset" "0x00800000" "28.0 MB" "InstructionDataOffset" "0x02400000" "4.0 MB" "ConvWeightDataOffset" "0x02800000" "4.0 MB" "FCWeightDataOffset" "0x02c00000" "4.0 MB" "EndOffset" "0x03000000" "Total: 48.0 MB"
To deploy the network on the Intel Arria 10 SoC hardware, run the deploy function of the
dlhdl.Workflow object. This function uses the output of the compile function to program the FPGA board by using the programming file. It also downloads the network weights and biases. The deploy function starts programming the FPGA device, displays progress messages, and the time it takes to deploy the network.
### FPGA bitstream programming has been skipped as the same bitstream is already loaded on the target FPGA. ### Loading weights to FC Processor. ### FC Weights loaded. Current time is 28-Jun-2020 13:45:47
To load the example image, execute the predict function of the
dlhdl.Workflow object, and then display the FPGA result, enter:
inputImg = imread('five_28x28.pgm'); imshow(inputImg);
Run prediction with the profile 'on' to see the latency and throughput results.
[prediction, speed] = hW.predict(single(inputImg),'Profile','on');
### Finished writing input activations. ### Running single input activations. Deep Learning Processor Profiler Performance Results LastLayerLatency(cycles) LastLayerLatency(seconds) FramesNum Total Latency Frames/s ------------- ------------- --------- --------- --------- Network 49243 0.00033 1 49807 3011.6 conv_module 25983 0.00017 conv_1 6813 0.00005 maxpool_1 4705 0.00003 conv_2 5205 0.00003 maxpool_2 3839 0.00003 conv_3 5481 0.00004 fc_module 23260 0.00016 fc 23260 0.00016 * The clock frequency of the DL processor is: 150MHz
[val, idx] = max(prediction); fprintf('The prediction result is %d\n', idx-1);
The prediction result is 5