HDL Verifier enables you to reuse your system-level design environment in your HDL design and verification environment for FPGAs and ASICs. You can test and verify RTL designs against golden reference models in MATLAB and Simulink, debug designs using HDL simulators, and generate testbenches and verification IP.
Use HDL cosimulation to verify ASICs and FPGAs with testbenches that run in MATLAB and Simulink with RTL code that runs in your HDL simulator. You can generate SystemVerilog DPI-C models from MATLAB, Simulink, and Simscape to perform functional verification using digital and mixed-signal simulation in HDL simulators. You can also generate Universal Verification Methodology (UVM) components from MATLAB and Simulink for production workflows or generate SystemC TLM 2.0 Transaction Level Models (TLMs) from Simulink models for virtual platform simulation. All these capabilities are compatible with existing HDL code and code generated by HDL Coder.
RTL Verification of ASICs and FPGAs
Verify HDL code with MATLAB and Simulink testbenches through cosimulation with simulators from Cadence®, Synopsys®, Siemens®, and AMD®. Export testbenches for SystemVerilog verification environments.
Cosimulation with Simulink
Verify HDL code using Simulink models as testbenches. Incorporate existing HDL code into system simulations through cosimulation with Xcelium™, VCS®, Questa™, and Vivado® HDL simulators.
Cosimulation with MATLAB
Use MATLAB for complex stimulus generation and to perform postprocessing in MATLAB testbenches for HDL simulators. Conversely, use MATLAB to create behavioral component models for simulation with Questa, Xcelium, or VCS HDL simulators.
Documentation (MATLAB Testbench, MATLAB Component) | Examples
Mixed-Signal Design and Verification
To evaluate how a design under test interacts with analog circuits, create behavioral models as stand-ins for analog functionality by generating SystemVerilog DPI-C code from analog or mixed-signal models from Simscape, SerDes Toolbox, or Mixed-Signal Blockset.
Examples (SerDes Toolbox, Mixed-Signal Blockset)
Export SystemVerilog Testbenches
Use ASIC Testbench to generate SystemVerilog DPI components from MATLAB functions or Simulink subsystems for use in functional verification environments, including VCS, Xcelium, Questa, and Vivado.
MATLAB: Documentation | Examples
Simulink: Documentation | Examples
Export UVM Testbenches
Use ASIC Testbench to generate complete Universal Verification Methodology (UVM) testbenches for HDL simulators from MATLAB and Simulink. Generate fully functional testbenches for the UVM framework.
Generate SystemC TLM 2.0 Transaction-Level Models
Use ASIC Testbench to generate SystemC virtual prototype models with TLM 2.0 interfaces for use in virtual platform simulations. Generate IP-XACT files with mapping information between Simulink and generated TLM components.
Product Resources:
Allegro MicroSystems Accelerates Chip Verification with MathWorks and Model-Based Verification
Allegro MicroSystems shifts left IC verification, shortening IC/ASIC verification time and enabling collaboration between design verification engineers and system designers.
HDL Verifier FAQs
HDL Verifier enables testing and verifying RTL designs against golden reference models in MATLAB and Simulink, debugging designs in simulators, and generating testbenches and verification IP for FPGA, ASIC, and SoC designs.
HDL Verifier supports cosimulation with Xcelium, VCS, Questa, and Vivado HDL simulators from Cadence, Synopsys, Siemens, and AMD, respectively.
Yes, HDL Verifier is compatible with both existing HDL code and code generated by HDL Coder, allowing you to verify both handwritten and generated HDL designs.
Yes, HDL Verifier can generate Universal Verification Methodology (UVM) components and complete UVM testbenches from MATLAB and Simulink for use in SystemVerilog verification environments.
ASIC Testbench is a feature that generates SystemVerilog DPI components, complete UVM testbenches, and SystemC TLM 2.0 transaction-level models from MATLAB functions or Simulink subsystems for use in functional verification environments.
Yes, HDL Verifier can generate SystemVerilog DPI-C code from analog or mixed-signal models created with Simscape, SerDes Toolbox, or Mixed-Signal Blockset to evaluate how designs interact with analog circuits.
Interested in HDL Verifier?
What's Next?
Panel Navigation
SUPPORT PACKAGE
