How to Prototype FPGAs for Motor Control

In the "Deploying Motor Control Algorithms to FPGA" videos, we give an overview of the reasons why control engineers are having to look beyond the use of traditional embedded controllers. Electrification, adoption of wideband materials such as silicon carbide and gallium nitride, and developing high-precision robots are some of the reasons engineers developing high-frequency switching algorithms for power and motor control are considering FPGAs and system on chip or SoC devices.

In the "Getting Started" video, we introduced how control engineers using Simulink can implement the control algorithms on the FPGA fabric. The workflow we introduce to target SoC devices was to use Simulink's HDL-compatible blocks to develop and design the algorithm and partition the model into parts that need implementing on the processor and the FPGA fabric. Finally, using MathWorks' advanced automatic code generation tools, generate the C and HDL code and integrate the system with AXI drivers, enabling the processor to control and access the FPGA of the system on chip device.

In this video, we will showcase the Trenz Electronic Motor Control Development Kit to showcase hardware prototyping. We will deploy a field-oriented control, or FOC, algorithm on the Xilinx Zynq UltraScale+ SoC device to control a permanent magnet synchronous motor. We will run the Simulink model to explore the behavior of the controller, partition the controller algorithm for software and hardware implementations, generate the C code and HDL code, deploy the bitstream to the hardware logic, and run the model on the ARM processor to operate the motor. Finally, we will compare the log signals of simulation against the hardware.

Before showcasing the workflow, a quick overview of the Trenz Electronic Motor Control Development Kit hardware. The Trenz Electronic Hardware is a modular kit consisting of the system on chip device module, a carrier board, and the motor driver module. Also included in this kit is a 24-volt rated, 4000 RPM, 53-watt brushless DC motor, which includes a 1,250 rev counter single ended encoder. Other accessories provided along with the kit, a 5-volt input power supply, an 8 GB micro SD card, and four-way plugs to connect to the board.

To power the motor driver module, Trenz Electronics recommends a bench power supply with its current limited. But for the purpose of this demonstration, a 24-volt MWA100 Series with an output current of 4.2 amps will be sufficient. For this video, the SoC device module will be the Xilinx Zynq UltraScale+. Support for the Zynq-7020 Series is also available. For more information on the Trenz kit and the support available from MathWorks, please visit the links provided.

For the purpose of the demonstration, we will look at a field-oriented control algorithm modeled in Simulink which has been partitioned. Running the simulation of the space vector modulation for the permanent magnet synchronous motor, we observe the transition of the control from open loop to closed loop operation, searching for a valid rotor position, and changing the speed and torque during the closed loop operation. The partition of the model is done such that the user interfaces, mode scheduler, and the low-rate outer loop that controls the velocity is run on the embedded processor, while the core controller recording high-speed switching, which calculates the voltage and sends out the driver signal, is implemented on the FPGA programmable hardware.

The main current controller consists of two proportional integral controller. Clarke, Park, and their respective inverse transforms convert between the stationary and rotating synchronous streams. The space vector modulator transforms the phase voltage commands into pulse-width modulation signals, which are applied to the stator windings. In this prototyping example, the high-rate inner loop will be implemented on the FPGA logic, resulting in a faster and more responsive PWM switching, as the FPGAs can run in the megahertz region.

To implement the model on the hardware, we will first set up the hardware if not already done. MathWorks supports many popular hardware boats from Xilinx, Intel, and Microsemi. And to make it easy to set up and configure, hardware support packages are available as add-ons to download. The Xilinx Zynq Support Package guides you through registering, configuring, and connecting your hardware board. Using the Embedded Coder Support Package along with the HDL Coder Support Package for Xilinx Zynq platform, we can deploy and run the executable on the Xilinx Zynq UltraScale+ platform. This automates the hardware setup, ensuring Ethernet connectivity and download of MathWorks firmware image on the SD card.

To set up the hardware, follow the complete guide provided in the MathWorks documentation "Getting Started with Targeting Xilinx Zynq Platform." This document uses the example of a Xilinx Zynq ZC702 Evaluation Kit. Use this as a guide to set up the Trenz Motor Control Development Kit. With the hardware set, using MathWorks advanced code generation capability, we will first generate the C code for the focZynqC model subsystem. Embedded Coder generates C code which is portable and can be integrated with any floating point embedded processor that uses ANSI C compiler. For more information on the Embedded Coder and its capabilities, please refer to the Embedded Coder product page and numerous resources on the MathWorks website.

From the focZynq HDL model subsystem, using the HDL Workflow Advisor, we will generate the HDL IP code. The HDL Workflow Advisor IP Code Workflow automates the steps that generate the HDL IP code, designed to connect with the embedded processor and perform synthesis tasks invoking a supported third party synthesis tool. Under the device target, we will choose the relevant Trenz device from the dropdown. The next two tasks sets the target reference design and defines the target interface. Think of the target reference design as the blueprint of the SoC device. The reference design defines different components on the board, such as ADC, PWM, LEDs, and input/output peripherals, such as I2C, SPI, et cetera.

Reference Design enables deployment of HDL IP on the FPGA hardware fabric and interface with the processor on the SoC board. Setting the target interface enables the processor to access the HDL code via Advanced eXtensible Interface, or AXI Interface, to read and write data to and from the IP code. This capability allows for tuning parameters on the FPGA and Simulink external mode, which is beneficial for prototyping.

The synchronization between the processor and the FPGA is based on the modes that can be used. Free running, where the processor and the FPGA run non-synchronized, continuously, and in parallel. Coprocessing/blocking, where the processor and the FPGA will run in tandem. Here, we'll choose free running. The port name, port type, and data type are automatically populated from the Simulink model.

The Target Platform Interface dropdown option allows you to map focZynq HDL ports to AXI Interface. AXI4 Interface is used to transfer a large chunk of data from the processor to the FPGA fabric and is used as input and output ports, as they are much faster and suited for data part of an algorithm. For control signals and parameter tuning, use the AXI-Lite option.

Task 3.2 in the HDL Workflow Advisor generates the HDL code and generates reports that provide information on the number of resources that have been used and provides a traceability report. The traceability report maps your source model and the generated HDL code using hyperlinks to navigate each line of HDL code to and from the Simulink model

Embedded System Integration task 4.0 integrates the generated HDL IP code with the embedded processor. To interface the processor to the generated HDL IP code, task 4.2 creates a Simulink model that replaces the original focZynq HDL subsystem with its equivalent AXI driver block. The Workflow Advisor, using Embedded Coder, automates the generation of the drivers that connect to the target hardware, giving read and write capability. Embedded Coder generates the AXI address mapping information, which is included in the C header file. The HDL IP inserted into the reference design is used to generate an FPGA bitstream for the SoC hardware in task 4.3.

And in task 4.4, we program the target device. Using the Generated Software Interface Model, you can run the model on the ARM processor in the Zynq UltraScale+ in Simulink external mode. This capability lets you monitor and tune the algorithm while it runs on hardware and link with the Simulink model on the first computer through an Ethernet connection.

Comparing the log signals from the simulations of the algorithm model and the hardware prototyping, the encoder calibration mode, the signals initially differ, then agree since the simulated and real motors started with different rotor positions. This workflow lets you deploy your design ideas on a hardware board and interface it to the software. If your design does not meet your requirements, you can repeat the workflow with a modified model or a different partition configuration. Visit the MathWorks Hardware Support page to get started with the Trenz Electronic Motor Control Development Kit and find resources related to topics discussed here.