SoC Blockset (for AMD)

Develop applications for AMD Versal and Zynq Adaptive SoCs and FPGAs

SoC Blockset (for AMD) enables you to design, simulate, deploy, and verify applications on AMD FPGAs and Adaptive SoCs. Using MATLAB and Simulink, the product provides hardware/software co-design workflows that target AMD devices on off-the-shelf and custom boards. You can model hardware and software applications, perform bit-accurate simulation, generate IP cores (with HDL Coder), build embedded software (with Embedded Coder), and program development boards using AMD Vitis™.

SoC Blockset (for AMD) enables HDL Coder to generate synthesizable C++ from MATLAB code for Vitis HLS and RTL from Simulink models with Vitis Model Composer blocks. You can perform hardware-in-the-loop (HIL) testing on designs deployed to development boards and verify deployed designs using MATLAB and Simulink testbenches.

The product includes reference designs for communications, vision, deep learning, and control applications for Versal™, Zynq™ UltraScale+™ MPSoC/RFSoC, and Zynq-7000 devices, and for AMD FPGAs.

Simulating Designs for Versal Adaptive SoC Devices

Block diagram of 5G N R S I B 1 recovery for F R 1 and F R 2.

5G and SDR Applications

With Wireless HDL Toolbox, simulate and deploy a 5G NR MIB recovery algorithm or a 5G NR SIB1 recovery algorithm for FR1 and FR2 using an SoC Blockset (for AMD) implementation. Use Zynq-based radios with Analog Devices RF cards to prototype, verify, and test practical wireless systems.

Documentation | Examples

Simulink model of a lane detection algorithm with an A M D Z C 706 board.

Vision Applications

Build models using SoC reference designs that enable capturing live video to simulation, processing video streams on hardware, and integration with deep learning processors.

Documentation | Examples

Block diagram and S o C Blockset (for A M D) model for a field-oriented control algorithm.

Motor and Power Electronics Controls Applications

Model and simulate motor and power electronics controllers partitioned between processors and programmable logic. Automate C code generation and compilation along with IP core generation to target AMD Zynq and Versal devices.

Documentation | Examples

Versal A I Core series V C K 190 evaluation kit hardware.

Target Versal Devices

Generate IP cores from algorithms with AXI4 interfaces (with HDL Coder) and deploy them to programmable logic. Generate software applications and device drivers (with Embedded Coder) for AXI4 communication. Automate customized boards, daughter cards, operating systems, and IP. Target Versal AI Engines with SoC Blockset (for AMD) and AMD Vitis™ Model Composer.

Documentation | Examples

Target RFSoC Devices

Simulate and deploy radar applications targeted to AMD RFSoC devices. Deploy 5G signal detection algorithms to RFSoC boards using SoC Blockset (for AMD) to program the hardware, load test data into memory, and control the deployed design. Implement frequency-hopping algorithms for CDMA and FHSS applications with AMD UltraScale+ RFSoCs.

Documentation | Examples (Wireless Communications, Radar)

Clockwise from left: Z C 706, ZedBoard, Arty, Z C 702, and PicoZed.

Target AMD UltraScale+ MPSoC and Zynq-7000 Devices

Develop applications such as motor/power electronics controls or wireless communications for implementation on MPSoC and Zynq-7000 platforms.

Documentation | Examples

Screenshot of the Hardware Setup app for AMD boards.

COTS Boards and Custom Board Support

Use the OS Customizer tool to modify and add libraries to the Linux^® distribution for your embedded processor. Customize the embedded Linux operating system of supported boards.

Documentation | Examples

Hardware/Software Co-Design

Model DDR memory and simulate shared memory transactions between hardware logic and embedded processors. Configure DMA controllers to arbitrate memory traffic. Account for memory latency and throughput in simulation.

Documentation | Examples

F P G A reference design with D D R memory interfaces and H D L Workflow Advisor target interface configuration.

Generate HDL Coder Reference Designs

Generate HDL Coder reference designs directly from SoC Blockset (for AMD) models, then use the HDL Workflow Advisor tool to integrate IP cores created with HDL Coder.

Documentation | Examples

Product Resources:

Documentation Examples Functions Blocks Hardware support Requirements Release notes

SoC Blockset FAQs

SoC Blockset (for AMD) is a MATLAB product that enables you to simulate and analyze the performance of algorithms on programmable SoCs and ASICs, then deploy them as hardware and software applications for prototyping and production.

SoC Blockset (for AMD) supports AMD Versal Adaptive SoCs, Zynq UltraScale+ MPSoCs/RFSoCs, and Zynq-7000 SoCs.

The SoC Builder app automates deployment by building IP cores and software, then programming development boards using HDL Coder and Embedded Coder.

Yes, you can build Simulink models of hardware architectures and simulate algorithms with hardware effects to identify performance issues such as latency and data loss before implementing on actual hardware.

SoC Blockset (for AMD) lets you build models that define interfaces between Arm processor cores, hardware logic, memory, and peripherals, allowing you to analyze implementation trade-offs when partitioning algorithms.

You can develop 5G and SDR applications, vision applications with live video processing, motor and power electronics controls, radar applications, and wireless communications systems.

Yes, SoC Blockset (for AMD) allows you to model DDR memory and simulate shared memory transactions between hardware logic and embedded processors, accounting for memory latency and throughput.

SoC Blockset (for AMD) analyzes applications running on hardware with performance diagnostics and software profiling tools that measure latency, bandwidth, and other metrics.