You can use the
socExportReferenceDesign function to generate a reference design from an
SoC Blockset™ model and avoid the manual steps required to generate and register a custom
reference design. The function generates these artifacts.
Board registration files
Reference design registration file
SoC models can be one of these types.
An SoC Model with an FPGA, memory, and optional I/O (no processor)
An SoC Model with a processor, FPGA, memory, and optional I/O
When exporting a custom reference design from an SoC model, the reference design does not include the design under test (DUT) and the interface to the DUT is exposed. After generating the reference design, you can integrate your custom IP by using the HDL Workflow Advisor tool. Your custom IP must have the same interface as the FPGA Algorithm block.
To export a custom reference design, first create an SoC model to model the system and the I/O available on your board. To create an SoC Blockset model, use one of these methods.
Include a DUT subsystem in the model. This subsystem must have the same interface as the IP core that you are developing. Because the generated reference design does not include the DUT subsystem, the DUT can be a simple model or just a pass-through block.
You can use the MATLAB as AXI master feature in the exported reference design to interact with the SoC device from the host. In Simulink®, open the Configuration Parameters dialog box by clicking Model Settings on the Modeling tab, and on the left pane, select Hardware Implementation. Then, expand Target hardware resources, select FPGA design (top-level), and then select Include 'MATLAB AXI Master' IP for host-based interaction.
In the IP core clock frequency (MHz) box, specify the IP core clock frequency in MHz.
To ensure that your SoC model supports code generation, use the SoC Builder tool to generate executables and deploy your model. For more information about the SoC Builder tool, see Generate SoC Design.
For an example showing this workflow on an FPGA-only case, see Export Custom Reference Design.
A device tree (DT) is a data structure that describes the hardware to the operating system. When you add an IP to the design, you should generate a new device tree so that the operating system can access the IP.
If your model contains both FPGA and processor subsystems, these additional steps are required before exporting the reference design.
In the configuration parameters , click Hardware Implementation on the left. Then, expand Target hardware resources, and select Include processing system in FPGA design (top-level).
Run the SoC Builder tool, follow the guided steps for code
generation, and then load the binaries to the FPGA. This step is required
because SoC Builder automatically generates a device tree file
.dtb) on the SD card named
hdlcoder_rd/soc_prj.output.dtb and a software model with
matching device names.
Copy the device tree file from the folder
the root folder of the SD card. In the generated
file, the custom device tree file is specified
hRD.DeviceTreeName = 'soc_prj.output.dtb';
Export the custom reference design for your model by using the
socExportReferenceDesign function. For example, for a model
soc_image rotation, enter this code at the MATLAB® command prompt.
The function generates these artifacts in the current folder.
Board registration files
Reference design registration file
Add the generated folder to the MATLAB path. Use the HDL Workflow Advisor tool to guide you through the steps for integrating your IP and generating hardware and software executables for deployment on an SoC device.
For an example showing the full workflow on an FPGA-only case, see Export Custom Reference Design. If your model includes a processing system, these additional steps are required when using the HDL Workflow Advisor tool.
In Simulink, right-click the DUT block that you want to integrate into the
reference design, and select HDL Code > HDL Workflow Advisor to open the HDL Workflow Advisor tool.
Alternatively, use the
hdladvisor (HDL Coder) function.
In step 1.1, set Target workflow to
IP Core Generation and Target platform to the platform generated by the
Click Run This Task to run the Set Target Device and Synthesis Tool task.
In step 1.3, set the target interface by connecting each port in your IP to the corresponding port in the reference design.
Click Run This Task to run the Set Target Interface task.
Continue with the remaining steps of the HDL Workflow Advisor tool.
Optional: In step 4.2, you can choose to generate a software interface model with IP core driver blocks (requires an Embedded Coder® license). If you choose to generate this software interface model, clear Skip this task under Generate a software interface model with IP core driver blocks for C code generation.
For more information, see the section titled "Generate a software interface model" in Getting Started with Targeting Xilinx Zynq Platform (HDL Coder).
The generated software interface model contains AXI driver blocks that match
the interface of the DUT subsystem. The device name is set to
'/dev/mwipcore' by default. Change the device name in
these AXI driver blocks to match the in the device tree file used by the SD card
There are several ways to find the device name:
The device name is derived from the DUT name of the SoC model. If you
export a reference design using an SoC model with the DUT name specified
'soc_hwsw_stream_fpga/FPGA Algorithm Wrapper',
the generated device name in the AXI driver blocks is
Find the device name in your operating system (OS) image after booting the SoC device. To do that, login to the board using UART or SSH protocols, and execute:
In step 4.4, set Programming method to Download.
When the HDL Workflow Advisor tool is done building, it returns a generated bitstream file. Program the FPGA with the generated bitstream file.
You can now deploy the software interface model in standalone mode, or use it in external mode to interact with the SoC device. For an example, see the section titled "Run the software interface model on Zynq ZC702 hardware" in Getting Started with Targeting Xilinx Zynq Platform (HDL Coder).