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Pham Van Dung


Last seen: 8 månader ago |  Active since 2012

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'viterbi_modelsim.mdl' does not exist.
Dear, I tried to open command "viterbi_modelsim" in the help documents of mathwork: http://www.mathworks.com/help/hdlverifie...

mer än 9 år ago | 1 answer | 0

1

answer

Question


Errors : algebraic loop in use HDL simulink coder
Dear friends, when i convert one Simulink block to Verilog use HDL Simulink coder, i have this problem: *_ Failed Cannot conn...

mer än 11 år ago | 2 answers | 0

2

answers

Question


Lookup Table with > 30 dimensions(n-D Lookup Table)
Dear friends, In generaly, 1 The n-D Lookup Table has maximum n=30 dimensions. I want to implement 1 n-D Lookup Table has ...

mer än 11 år ago | 0 answers | 0

0

answers

Answered
How to generate synthesizable VHDL from Simulink block?
Dear, 1. We can't implement double datatype in FPGA. Tim McBrayer is right. std_logic_vector, signed, or unsigned is support ...

mer än 11 år ago | 0

Question


How to creat many HDL blocks at one time
Dear my friends! I have a question need your helpings! I have 3 simulink blocks, and i want to convert them to verilog code, ...

mer än 11 år ago | 1 answer | 0

1

answer

Question


Error beetween two methods: Simulink and Verilog(after convert by HDL coder)
Dear My friends! Now i have some problems in HDL simulink coder that need your helping. When i convert my code from simulink...

mer än 11 år ago | 1 answer | 0

1

answer

Answered
How to test the HDL coder generated code with Modelsim?
Chao Nam, hien tai minh cung dang nghien cuu ve HDL coder, co gi lien he voi minh nhe, dungdkt27@gmail.com

mer än 11 år ago | 0

Question


Simulink HDL coder Results compare
Dear my friend, I have a simulink subsystem that have one Gain block inside. I used HDL Simulink Coder to convert to verilog ...

mer än 11 år ago | 1 answer | 0

1

answer

Question


About HDL simulink coder for StateFlow
Dear friends, I have a Stateflow subsystem that i have used a event.The event is a trigger input with frequency = 400ns( I used...

ungefär 12 år ago | 1 answer | 0

1

answer

Question


About HDL simulink coder
Dear friends, I have an error when I try to convert StateFlow Block to Verilog: _* Failed network:propagateClockRate:ratesDon...

ungefär 12 år ago | 2 answers | 0

2

answers

Question


about error in stateflow
dear, when i implement stateflow in block to mult or add signals in stateflow, i have this error: _Cannot solve algebraic ...

ungefär 12 år ago | 1 answer | 0

1

answer

Question


about HDL supported libraries
Dear, I have a problem in Simulink HDL Coder : Can i extend the supported HDL library of Simulink HDL Coder Tools? And if i ...

ungefär 12 år ago | 1 answer | 0

1

answer

Question


Creat Signal in Simulink
Dear, I have a signal that i have saved in my workspace with the name is Matlab.mat This is my result of the previous simul...

mer än 12 år ago | 2 answers | 0

2

answers

Question


Truth table in staflow
Dear, I have a problem when i want to define a Underspecified Truth Table like: <http://www.mediafire.com/myfiles.php> Than...

mer än 12 år ago | 0 answers | 0

0

answers

Question


HDL simulinks coder support
Dear friends, I have a problem MATLAB Function. How do I generate HDL Code for my MATLAB Function in Simulink HDL Coder (R2011b)...

mer än 12 år ago | 2 answers | 0

2

answers

Question


HDL simulinks coder error
Dear Tim McBrayer, When I tried to convert my Simulink file to VHDL code and I used HDL Workflow Advisor, but in step 3.2: Ge...

mer än 12 år ago | 1 answer | 0

1

answer

Question


HDL simulinks coder about
Dear friends, I have a problem MATLAB Function. How do I generate HDL Code for my MATLAB Function in Simulink HDL Coder (R2011...

mer än 12 år ago | 1 answer | 0

1

answer