HDL Coder won't map LUT into BRAM

Hello everyone.

I am trying to implement a machine learning algorithm into an FPGA using HDL Coder. I was recommended to use LUT blocks to implement the data in the design, as it would be mapped to the BRAM in the FPGA.

Once I run HDL Workflow Advisor, all the steps seem to go well. However, when I look at the report of Place and Route step, BRAM and ROM is at 0%, so I'm not sure if this is working as intended.

Does someone have any idea? I will attach a sample design along with the data.

Thank you very much.

Answer 1

[Shomit Dutta]

Hi Joaquin,

As seen in the figure in your question, the input to the LUT is a constant and thus Xilinx synthesis tool will optimize the LUT. If you have a non-constant input to the LUT, synthesis tool will infer a RAM.

Thanks,

Shomit