The validation model generated by HDL Coder only compares the original DUT model against changes due to area and timing optimizations during code generation. It does not compare the original DUT against changes due to IP core interface generation.
When using the IP Core generation workflow, HDL Coder generates additional translation logic between the DUT boundary and the AXI interfaces. When using the AXI4 or AXI4-Lite interface you do not need model the entire protocol. Instead, you only need to model the data port for the interface. When you map a port to AXI4 or AXI4-Lite, HDL Coder generates an AXI accessible register and connects it to the port. This allows you to write/read data to/from the register and access FPGA logic.
The additional translation logic between the AXI interface and DUT boundary inserted by HDL Coder is not captured by the validation model. Therefore, the strobe register, other generated registers, and AXI protocol signals are not part of the validation model.
Unfortunately, we do not have a way at this time to add this additional logic to the validation model, but I have captured your request. You would have to add this additional logic in the validation yourself to have it be represented. An alternative verification method to consider is using UVM test bench generation from HDL Verifier. This lets you use the AXI-based protocols in your test bench. An example following that approach can be found here:
To learn more about the validation model, see this page: