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Error with cosimulation on tunable parameters

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kimi
kimi on 1 Dec 2020
Answered: Kiran Kintali on 8 Dec 2020
Hello all!
I'm having trouble with conducting FPGA In the Loop. I'm getting this error regarding cosimulation and tunable parameters. Do you know of a solution or a bypass? The objective is to do a FPGA in the loop simulation of a field oriented control based current controller.

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Answers (2)

Kiran Kintali
Kiran Kintali on 2 Dec 2020
This is a limitation in the cosimulation test bench generation.
Can you consider using stand-alone testbench with HDL Simulator?

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kimi
kimi on 8 Dec 2020
Ok. Is there no way for me to integrate the Zedboard? Can I do FPGA data capture?

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Kiran Kintali
Kiran Kintali on 8 Dec 2020
yes, You can target zed board using HDL Coder. FPGA data capture is another good way to capture signals. please contact support@mathworks.com

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