Dear friends, I have a Stateflow subsystem that i have used a event.The event is a trigger input with frequency = 400ns( I used Pulse Generator block in simulink ). I try to convert this subsystem to Verilog code by HDL simulink coder and it's have a error:
Error: Cannot support triggered sample time in 'Stateflow/Sub/400n/'
How can I solve this problem, Can you give me some ideal to convert my code.
Need for helping! Thanks alot!
Pham Van Dung