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About HDL simulink coder for StateFlow

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Pham Van Dung
Pham Van Dung on 25 Nov 2012
Answered: Kiran Kintali on 1 Nov 2020
Dear friends, I have a Stateflow subsystem that i have used a event.The event is a trigger input with frequency = 400ns( I used Pulse Generator block in simulink ). I try to convert this subsystem to Verilog code by HDL simulink coder and it's have a error:
Error: Cannot support triggered sample time in 'Stateflow/Sub/400n/'
How can I solve this problem, Can you give me some ideal to convert my code.
Need for helping! Thanks alot!
Pham Van Dung


Tim McBrayer
Tim McBrayer on 21 Jun 2013
What kind of block has the error reported for it? Is the reported block from within a Stateflow chart? Is the Stateflow chart inside a triggered subsystem? Have you experimented with using an input event to the Stateflow chart instead of a triggered subsystem (if the latter is what you are doing?)

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Answers (1)

Kiran Kintali
Kiran Kintali on 1 Nov 2020
Attached model describes how to model either edge in Stateflow suitable for HDL code generation.
HDL Verision
Result Comparison


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