timing loops found by synthesis tool when using sqrt function block in hdl coder

Hello,

I have designed a control system in Simulink and now I am trying to port the algorithm to a FPGA by using the HDL Coder (Matlab 2017b). The target is a Zedboard with the z-7020 SoC. The synthesis tool is Vivado (version 2016.4).

Within the design there are a few math operations, including the calculation of square roots. I used the square root block that can be found in the Simulink library (HDL Coder/Math Operations). Whenever I generate code and start the synthesis in Vivado, i receive critical warnings concerning timing loops (called "combinational loops" in the timing report). It appears that these are produced by the square root functions, as Vivado detects the loops in the generated source code of the square root functions. However, when I design a simple model that only includes sources that are connected to the square root blocks, no timing loops occur.

After the implementation of the actual control system in Vivado, the utilization of LUT, DSP etc. is below 80% for each category, so I assume it is not an issue of too little resources of the FPGA. For both cases, the simple model and the actual model have the same clock frequency.

Does anyone know why these critical warnings appear?

Answer 1

[Kiran Kintali]

This is now fully resolved in R2020b release. Sqrt operation is fully pipelined and several custom latency options for a range of application requirements. Please do share your model if you continue to have any timing violation during synthesis.

https://www.mathworks.com/help/hdlcoder/release-notes.html

Block Enhancements

Optimized Square Root: Generate high-frequency fixed-point HDL implementation of square root operations

When you use the SqrtFunction architecture of the Sqrt block with fixed-point data types, you can now use the LatencyStrategy and CustomLatency settings in the HDL Block Properties dialog box to specify whether to use zero, maximum, or a custom latency value between zero and maximum value. You can use the custom latency implementation to choose from a range of frequency values.

Depending on the UseMultiplier and LatencyStrategy settings, you can use a pipelined multiplication algorithm or a shift and add algorithm to compute the square root. See Implement Control Signals Based Mathematical Functions Using HDL Coder.

[Morris]

To be honest, I didn't expect any answer anymore and figured out a workaround in my algorithm. Anyways, I appreciate the reply and effort and will keep your provided info in my mind. Thanks.