Using Reference Model for HDL code Generation
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Kamyar Khosravi on 10 Apr 2018
Is there anyway to generate HDL code for a reference model . For example, let's say I have a subsystem that I would like to use across my design. There are currently two problems with repeating the same subsystem across the model. One is that the generated code outputs different Verilog files for each of the called subsystem. Second is that if I want to make a change to the subsystem, the change will not happen across the other subsystems. Is there a way to create a subsystem, that can be modified globally and at the same time generate only one Verilog file?
Many thanks, Kamyar
More Answers (1)
Tim McBrayer on 10 Apr 2018
Mark each instance of the subsystem as atomic. When marked atomic, it will generate only one output file for all instances.
Secondly, you can place your subsystem in a library. When you use a library block, each copy refers back to the original library block. Changing the library block will cause every instance to have the same change.