How can I convert serial data to a binary sequence?

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> The sequence is 01011010 how can I change from the square wave shown here to a square wave that shows just 01011010? The data rate is 600 bits per second and I am sampling at about 3 times that. Thank you.
Walter Roberson
Walter Roberson on 17 Mar 2017
I was misreading the readings a bit.
On my display it appears that 3 cm corresponds to 80 samples. The overall display shows up as 7.8 cm, so that would be 7.8*(80/3) = 208 samples.
The sample counts would work out if there were 4 samples per bit rather than 3 -- 208/4 = 52 bits, which would be 6 1/2 repetitions of 8 bits. For the sample count to work out with 3 samples per bit, there would have to be between 8 and 9 repetitions rather than between 6 and 7.
Walter Roberson
Walter Roberson on 19 Mar 2017
I see in the other discussion that you are sampling at about 3000 samples per second. 208 samples at 3000 samples per second of 600 data bits per second would only be enough samples for 5 complete repetitions.
Question: are you sending async or synchronous? If you are sending async with RS232 then you need to worry about start bits and stop bits, and you have to know the number of each; pretty much everyone uses 1 start bit, but the number of stop bits used varies a bit. Asynch implies that the transitions need to be detected rather than assuming a fixed frequency.
It would also be important to know if you are using a protocol such as bisync or NRZ or NRZI.

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Accepted Answer

John BG
John BG on 24 Jun 2021
Edited: MathWorks Support Team on 24 Jun 2021
There are a couple ways to do this. The comments below are referring to John's initial Answer (Approach 2).
Approach 1:
For the first approach, we've included a Simulink model.
Convert this analog serial signal into a digital signal, we will use a comparator.  This will generate a series of 1s and 0s at “around 1800 Samples/second.”  Then we will down-sample, but since we don’t know the exact original sample rate we have used interp1() instead of downsample().  This has the added benefit of handling nonuniform input sample rates but requires a time value for each sample.  It generates our stream of 1s and 0s at 600 S/s.  We can get away with this because the incoming symbol rate is exactly 600 b/s, therefore sampling at that rate guarantees us one sample per symbol (bit).  More care may be needed to apply this approach to jittery signals.  Finally, we can do digital processing to recover the input signal. In this case, we know the first 8 elements of this sequence will be our input data word. Additionally, we can plot the first 9 elements to see a graphical representation (the extra element helps the graph look as expected).
Approach 2:
1) square the signal the time reference is not really needed. Clipping
2) Brendan, please let know if the following reasoning is consistent with your question:
in order to use the 600bps rate one has to know the time reference.
Visual observation reveals that about 15 samples make the 8 pulses of the basic sequence.
7 bursts take the whole scope shown, that comprises 2840-2640, 200 samples
200 samples are (approximately) 7*8=56 pulses
If you have assigned 1 bit per pulse, an estimate of the presented time span would be:
56[pulses]*1[bit/pulse]*1[sec]/600[bps]*200[samples]=15 seconds
it would be safer to assign at least 3 samples per pulse.
3) synchronisation, how do want to sync?
4) can you present a time based graph? with the time vector, not the numerals. Meaning, can you, instead of
If you find this answer useful would you please be so kind to mark my answer as Accepted Answer?
To any other reader, please if you find this answer
please click on the thumbs-up vote link
thanks in advance
John BG
John BG
John BG on 21 Mar 2017
if sync happened the previous word and missed, doesn't matter, the circuit should catch up on next word.
It's not about protocol, you are assuming that the step samples-to-bits is solved. The question was about basic amplitude conditioning, clipping solves it.
If it had been asked anything about sync
then there is only one word to sync to: 10110100 or 11010010 or 01101001 all same word shifted, also 01011010 but you make things a bit more difficult because of the lack of transition, the uncertainty of telling to sync in the middle of nowhere.
see it this way:
you are suggesting to apply a set of masks and tell whether the word is detected
buffer 7 bits; check mask 11010010
buffer 14 bits. check mask 1111001100001100
buffer 21 bits check mask 111111000111000000111000
I am suggesting
if up
if timeout break
if still up
if timeout break
if down
if timeout break
if up
if timeout break
if down
if timeout break
if still down
if timeout break
if up
if timeout break
if down
if timeout break
that, in real 3D, example circuit, the CY22150,
tolerated jitter:
timing is everything, within specs? bus caught? too fast, too slow, sync lost
the faster is the PLL clock the better because it widens lock windows
hope it helps
John BG
Walter Roberson
Walter Roberson on 21 Mar 2017
"if sync happened the previous word and missed, doesn't matter, the circuit should catch up on next word."
That depends on it being an asynch protocol, which we do not know. It might be a synchronous protocol.
Synchronous protocols have two basic variations:
A) synchronization is signaled (somehow), and for a period of time after that, clocks are assumed to stay in sync to within half of a bit time, so that the total timing difference between sender and receiver is less than 1 bit during the block. After that period, synchronization is re-established for another burst. If I recall correctly, I have heard this referred to as a "block sync protocol"
B) synchronization is continual and not block oriented. The protocol is arranged so that there is a guaranteed transition within a certain number of bits no matter what the source. This can be by "stuffing" a transition if needed that is removed from the data stream on the receiver; or it can be by using two or more different constellation encodings for groups of bits and switching to the alternate constellation if continuing in the same encoding would otherwise have failed the transition guarantee. Each transition regenerates the clock for the receiver, so instead of it being a fixed block size after a block sync during which the clock is considered to be valid, every received transmission effectively restarts a timer. This kind of protocol can go on indefinitely, but there are usually built in safeguards so that you can determine the initial boundary in the first place, and also safeguards to periodically re-establish the major boundary in case the link dropped. These often involve deliberate protocol violations.
"you are suggesting to apply a set of masks and tell whether the word is detected"
I am suggesting no such thing.
Async protocols typically have mandatory silence gaps, and extra non-data bits or extra transitions to set up framing for the following byte (which could be 5 to 11 data bits); or (much less commonly) framing for two bytes. Those mandatory silence gaps and extra bits or transitions leave visible traces on the signal. It is far from clear that we are seeing those traces here; we are not seeing the sort of traces that would be associated with RS232, RS422, or TTL, even if we were to suppose that the y axis has been mislabeled.
Synchronous protocols vary in how they handle timing and synchronization, but by definition for synchronous protocols, it is never at the bit or byte level. Any protocol that synchronizes each byte independently is, by definition, an asynchronous protocol.

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More Answers (1)

fateme zabihi
fateme zabihi on 8 Mar 2021
I have a 4-bit output as a pulse that I want to multiply by 8, 4, 2, and 1 based on the importance of the bits and see the final output. What should I do?


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