Discrete integrator again fails to convert to Verilog due to delay balancing failure

I'm trying to convert a discrete integrator block to Verilog and I'm getting the following error. I’m new to FPGA and don’t yet understand the numerous settings very well, but I’d like to figure out what’s going on. I managed to set discrete time everywhere, but I haven’t figured out this error yet. Please tell me.

Answer 1

[Kiran Kintali]

>> hdlsaveparams('integrator/Integrator')

fpconfig = hdlcoder.createFloatingPointTargetConfig('NATIVEFLOATINGPOINT');
hdlset_param('integrator', 'FloatingPointTargetConfiguration', fpconfig);
hdlset_param('integrator', 'GenerateValidationModel', 'on');
hdlset_param('integrator', 'HDLSubsystem', 'integrator/Integrator');

% adjust the OS value based on the ratio of data rate and clock rate; 
% % for this model a minimum latency of 11 based on latency of the double
% precision math in the feedback loop.
hdlset_param('integrator', 'Oversampling', 11);    % <===========
% enable clock rate pipelining on the model
hdlset_param('integrator', 'ClockRatePipelining', 'on') % <===========

hdlset_param('integrator', 'PackagePostfix', '_pac');
hdlset_param('integrator', 'ProjectFolder', 'hdl_prj');
hdlset_param('integrator', 'ResetInputPort', 'reset_x');
hdlset_param('integrator', 'TargetDirectory', 'hdl_prj\hdlsrc');
hdlset_param('integrator', 'TargetLanguage', 'Verilog');
hdlset_param('integrator', 'UseFloatingPoint', 'on');

hdlset_param('integrator/Integrator/Discrete-Time Integrator', 'LatencyStrategy', 'Max');

With CRP option on and with the right OS value you should be able to generate code.

>> makehdl('integrator/Integrator')
### Working on the model integrator
### Generating HDL for integrator/Integrator
### Using the config set for model integrator for HDL code generation parameters.
### Running HDL checks on the model 'integrator'.
### Begin compilation of the model 'integrator'...
### Working on the model 'integrator'...
### Working on... GenerateModel
### Begin model generation 'gm_integrator'...
### Rendering DUT with optimization related changes (IO, Area, Pipelining)...
### Model generation complete.
### Generated model saved at hdl_prj\hdlsrc\integrator\gm_integrator.slx
### Generating new validation model: 'gm_integrator_vnl'.
### Validation model generation complete.
### Begin Verilog Code Generation for 'integrator'.
### MESSAGE: The design requires 11 times faster clock with respect to the base rate = 0.001.
### Begin Verilog Code Generation for 'Integrator_tc'.
### Working on Integrator_tc as hdl_prj\hdlsrc\integrator\Integrator_tc.v.
### Code Generation for 'Integrator_tc' completed.
### Working on integrator/Integrator/nfp_add_double as hdl_prj\hdlsrc\integrator\nfp_add_double.v.
### Working on integrator/Integrator as hdl_prj\hdlsrc\integrator\Integrator.v.
### Code Generation for 'integrator' completed.
### Generating HTML files for code generation report at integrator_codegen_rpt.html
### Creating HDL Code Generation Check Report Integrator_report.html
### HDL check for 'integrator' complete with 0 errors, 1 warnings, and 1 messages.
### HDL code generation complete.
>> 

in R2024a if you don't set the sufficient Oversampling factor you should see this message...

>> hdlset_param('integrator', 'Oversampling', 10); % intentionally set this too low than latency requested/required in a feedback loop...
>> makehdl('integrator/Integrator')

Delay balancing unsuccessful. Cause:
   Clock-rate pipelining found at least one feedback loop using optimizations that exceeds the
   allowed latency budget(s). Consider either setting the oversampling factor to '11' to provide
   sufficient latency budget or decreasing the latency by reducing optimization requests

in R2024a if you disabled CRP option you should see this guidance message...

   >> hdlset_param('integrator', 'ClockRatePipelining', 'off') % intentionally turn CRP off for a model that requires latency in a feedback loop...
   >> makehdl('integrator/Integrator')
   
For the block 'integrator/Integrator/Discrete-Time Integrator'
   Delay balancing unsuccessful. Cause:
   An extra 10 cycles of latency introduced by optimizations in the feedback loop cannot be offset
   using design delays for the loop latency budget. If you are modeling at data rate (high-level
   description of algorithm without hardware implementation details), refer to the clock-rate
   pipelining report for more details. If you are modeling at clock rate, consider increasing the
   latency budget by adding more design delays in the feedback loop. Refer to the delay balancing
   report for more details. Offending block: integrator/Integrator/Discrete-Time Integrator

The messages and links should help you get to a working model.

[Andrew Sol]

I received the following messages. Is this critical?

Answer 2

[Kiran Kintali]

can you share the SignalBuilder.mat file?

[Andrew Sol]

Yes of course, here it is. I also tried replacing it with a regular constant, but nothing changed. The error has not gone away.