Is there anyway to test custom IP cores on MATLAB/SIMULINK

Hi,

I want to test my own IP core with MATLAB/SIMULINK. And I tried all ways of HDL tools but all encountered problems.

• In FPGA-in-loop test, it only supports HDL files rather than IP files (.xci)
• In HDL Verifier Cosimulation, it only supports Xilinx IPs (add .xci and its HDL wrapper). But I cannot use my own IPs. Always has this error: ERROR: [VRFC 10-2063] Module <IP_name> not found while processing module instance <your_instance_name>

Is it possible to test my custom IP?

Answer 1

[Kiran Kintali]

You can make a DUT with Simulink subsystems and combine them with your custom IP using Black box interface and the combined IP can be verified using these features.

https://www.mathworks.com/help/hdlcoder/run-and-verify-ip-core-on-target-hardware.html?s_tid=CRUX_lftnav

https://www.mathworks.com/help/hdlcoder/ug/create-host-interface-script-to-control-and-rapidly-prototype-hdl-ip-core.html

Create Host Interface Script to Control and Rapidly Prototype HDL IP Core

Rapidly prototype the HDL IP core by interfacing with your target board over Ethernet or JTAG. Use an Ethernet connection for boards that have an ARM® processor. Use a JTAG connection for boards that do not have an ARM processor.

[Zhengchen Guo]

Hi Kiran,

Thanks for your useful advice!

I read the above infos and am still confused. Does the IP have to be generated by the HDL coder containing AXI manager interface? Could I test the IP generated by other platform or the third-party?

[Angela Cuadros Castiblanco]

Hello Zhengchen,

To clarify, you can use the host interface script to test IP cores generated using HDL coder in MATLAB or Simulink. The links that Kiran provided give you an overview of how to use these scripts and how to generate them.

From your original question, you mentioned that you were interested in testing your own IP core. Like Kiran mentioned, you could use a blackbox to combine your custom IP (in the form of HDL files) into a DUT in Simulink. For this method you would need to include the hdl files of your custom IP in the "Additional Files" when generating your IP core. This example shows how to use a blackbox in IP core generation:

https://www.mathworks.com/help/hdlcoder/ug/ip-core-generation-of-an-i2c-controller-ip-to-configure-the-audio-codec-chip.html

Then you can go through the IP core generation workflow and generate the host interface script to test your IP core. Depending on your board and reference design, you can either use the HDL verifier JTAG AXI Manager IP or the ARM processor on your board to interface with your target board over Ethernet or JTAG.

If this does not answer your questions, could you elaborate more on your use case? That is, are you trying to do hardware in the loop simulation or cosimulation using ModelSim or similar tools? and could you provide an example of the IP that you would like to integrate in Simulink, if not could you elaborate on the format and files that constitute your IP?

Thanks!

Angela