For pure pixel in and pixel out based streaming interface DUT, the blocks such as frame to pixel and pixel to frame should be outside the FPGA/ASIC DUT. They are typically in the test bench portion reading the image/video and converting matrix/images to sample/pixels. See a basic HDL Coder example here
In Matrix/Frame based DUT workflows you can pass the matrix/image types directly into DUT and hence there is no need for these blocks in the testbench. See the examples in the IO optimization section here.
With Streaming Interface DUT modeling style you have 100% control on the pixel processing, all scheduling and marshalling of the pixel data is manual. With the Frame based modeling style and code generation you can model at high level of abstraction and use HDL Coder optimizations for HDL code generation.
